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2012-12-20Don't use isa<CallInst>(this) in the constructor for CallInst's base class.Richard Smith
This has undefined behavior, because the classof implementation attempts to access parts of the not-yet-constructed derived class. Found by clang -fsanitize=vptr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170658 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20[mips] Refactor conditional branch instructions with two register operands.Akira Hatanaka
Separate encoding information from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170657 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20fix most of remaining issues with large frames.Reed Kotler
these patches are tested a lot by test-suite but make check tests are forthcoming once the next few patches that complete this are committed. with the next few patches the pass rate for mips16 is near 100% git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170656 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20[mips] Use "or $r0, $r1, $zero" instead of "addu $r0, $zero, $r1" to copyAkira Hatanaka
physical register $r1 to $r0. GNU disassembler recognizes an "or" instruction as a "move", and this change makes the disassembled code easier to read. Original patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20Fix use-before-construction of X86TargetLowering.Richard Smith
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170654 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20Don't use -1 as a value of an unsigned 7-bit enumeration; that has undefinedRichard Smith
behavior and violates the !range constraints we put on loads of this enum. Found by clang -fsanitize=enum. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170653 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20[mips] Change the order of template parameters. Move the default parameters toAkira Hatanaka
the end. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170651 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20[mips] Refactor shift instructions with register operands. Separate encodingAkira Hatanaka
information from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170650 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20[mips] Refactor shift immediate instructions. Separate encoding informationAkira Hatanaka
from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170649 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20[mips] Refactor arithmetic and logic instructions with immediate operands.Akira Hatanaka
Separate encoding information from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170648 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20[mips] Refactor arithmetic and logic instructions. Separate encodingAkira Hatanaka
information from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170647 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20[mips] Delete ArithOverflowR and ArithOverflow and use ArithLogicR andAkira Hatanaka
ArithLogicI as the instruction base classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170642 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20Loop Vectorizer: Enable if-conversion.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170632 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20s/AttributesImpl/AttributeImpl/g This is going to apply to Attribute, not ↵Bill Wendling
Attributes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170631 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20Do not introduce vector operations in functions marked with noimplicitfloat.Bob Wilson
<rdar://problem/12879313> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170630 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20whitespaceNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170626 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20Target/R600: Update MIB according to r170588.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170620 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Add a context so that once we uniquify strings we can access them easily.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170615 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19MC: Add MCInstrDesc::mayAffectControlFlow() method.Jim Grosbach
MC disassembler clients (LLDB) are interested in querying if an instruction may affect control flow other than by virtue of being an explicit branch instruction. For example, instructions which write directly to the PC on some architectures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170610 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Refactor isIntrinsic() to be quicker, and change classof() (and thus, ↵Michael Ilseman
isa<IntrinsicInst>()) to use it. This decreases the number of occurrences of the slow-path string matching performed by getIntrinsicID(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170602 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19s/AttributeListImpl/AttributeSetImpl/g to match the namechange of AttributeList.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170600 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Add a missing 'else'. Found by grep '} if'Dmitri Gribenko
No testcase because it is apparently not so trivial to construct. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170595 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19R600: Remove unecessary VREG alignment.Tom Stellard
Unlike SGPRs VGPRs doesn't need to be aligned. Patch by: Christian König Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170593 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19R600: control flow optimizationTom Stellard
Branch if we have enough instructions so that it makes sense. Also remove branches if they don't make sense. Patch by: Christian König Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170592 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19R600: New control flow for SI v2Tom Stellard
This patch replaces the control flow handling with a new pass which structurize the graph before transforming it to machine instruction. This has a couple of different advantages and currently fixes 20 piglit tests without a single regression. It is now a general purpose transformation that could be not only be used for SI/R6xx, but also for other hardware implementations that use a form of structurized control flow. v2: further cleanup, fixes and documentation Patch by: Christian König Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170591 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Split out abbreviations for the skeleton info from the rest ofEric Christopher
the abbreviations. Part of implementing split dwarf. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170589 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Remove the explicit MachineInstrBuilder(MI) constructor.Jakob Stoklund Olesen
Use the version that also takes an MF reference instead. It would technically be possible to extract an MF reference from the MI as MI->getParent()->getParent(), but that would not work for MIs that are not inserted into any basic block. Given the reasonably small number of places this constructor was used at all, I preferred the compile time check to a run time assertion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170588 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Fix a bug that was found by building clang with -fsanitize.Nadav Rotem
I introduced it in r166785. PR14291. If TD is unavailable use getScalarSizeInBits, but don't optimize pointers or vectors of pointers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170586 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19LLVM sdisel normalize bit extraction of the form:Evan Cheng
((x & 0xff00) >> 8) << 2 to (x >> 6) & 0x3fc This is general goodness since it folds a left shift into the mask. However, the trailing zeros in the mask prevents the ARM backend from using the bit extraction instructions. And worse since the mask materialization may require an addition instruction. This comes up fairly frequently when the result of the bit twiddling is used as memory address. e.g. = ptr[(x & 0xFF0000) >> 16] We want to generate: ubfx r3, r1, #16, #8 ldr.w r3, [r0, r3, lsl #2] vs. mov.w r9, #1020 and.w r2, r9, r1, lsr #14 ldr r2, [r0, r2] Add a late ARM specific isel optimization to ARMDAGToDAGISel::PreprocessISelDAG(). It folds the left shift to the 'base + offset' address computation; change the mask to one which doesn't have trailing zeros and enable the use of ubfx. Note the optimization has to be done late since it's target specific and we don't want to change the DAG normalization. It's also fairly restrictive as shifter operands are not always free. It's only done for lsh 1 / 2. It's known to be free on some cpus and they are most common for address computation. This is a slight win for blowfish, rijndael, etc. rdar://12870177 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170581 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Transform (x&C)>V into (x&C)!=0 where possiblePaul Redmond
When the least bit of C is greater than V, (x&C) must be greater than V if it is not zero, so the comparison can be simplified. Although this was suggested in Target/X86/README.txt, it benefits any architecture with a directly testable form of AND. Patch by Kevin Schoedel git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170576 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19PowerPC: Expand VSELECT nodes.Benjamin Kramer
There's probably a better expansion for those nodes than the default for altivec, but this is better than crashing. VSELECTs occur in loop vectorizer output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170551 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Change AsmOperandInfo::ConstraintVT to MVT, instead of EVT.Patrik Hagglund
Accordingly, add MVT::getVT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170550 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Revert 170545 while I debug the ppc failures.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170547 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Add r170095 back.Rafael Espindola
I cannot reproduce it the failures locally, so I will keep an eye at the ppc bots. This patch does add the change to the "Disassembly of section" message, but that is not what was failing on the bots. Original message: Add a funciton to get the segment name of a section. On MachO, sections also have segment names. When a tool looking at a .o file prints a segment name, this is what they mean. In reality, a .o has only one anonymous, segment. This patch adds a MachO only function to fetch that segment name. I named it getSectionFinalSegmentName since the main use for the name seems to be infor the linker with segment this section should go to. The patch also changes MachOObjectFile::getSectionName to return just the section name instead of computing SegmentName,SectionName. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170545 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19[msan] Add track-origins argument to the pass constructor.Evgeniy Stepanov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170544 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Split the usage of 'EVT PartVT' into 'MVT PartVT' and 'EVT PartEVT'.Patrik Hagglund
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170540 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Change RegVT in BitTestBlock and RegsForValue, to contain MVTs,Patrik Hagglund
instead of EVTs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170538 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Change TargetLowering::getTypeForExtArgOrReturn to take and returnPatrik Hagglund
MVTs, instead of EVTs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170537 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT,Patrik Hagglund
from EVT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170536 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Change TargetLowering::RegisterTypeForVT to contain MVTs, instead ofPatrik Hagglund
EVTs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170535 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Change TargetLowering::TransformToType to contain MVTs, instead ofPatrik Hagglund
EVTs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170534 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund
of EVT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170532 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19[msan] Heuristically instrument unknown intrinsics.Evgeniy Stepanov
This changes adds shadow and origin propagation for unknown intrinsics by examining the arguments and ModRef behaviour. For now, only 3 classes of intrinsics are handled: - those that look like simple SIMD store - those that look like simple SIMD load - those that don't have memory effects and look like arithmetic/logic/whatever operation on simple types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170530 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Change TargetLowering::getTypeToPromoteTo to take and return MVTs,Patrik Hagglund
instead of EVTs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170529 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19LoopVectorize: Make iteration over induction variables not depend on pointer ↵Benjamin Kramer
values. MapVector is a bit heavyweight, but I don't see a simpler way. Also the InductionList is unlikely to be large. This should help 3-stage selfhost compares (PR14647). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170528 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT.Patrik Hagglund
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170524 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19X86ISelLowering.cpp: Fix warnings. [-Wlogical-op-parentheses]NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170523 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Change TargetLowering::getCondCodeAction to take an MVT, instead ofPatrik Hagglund
EVT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170522 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Inline hasFunctionOnlyAttrs into its only use.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170518 91177308-0d34-0410-b5e6-96231b3b80d8
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