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2010-08-12Fix comment orderBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110898 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12Begin to support some vector operations for AVX 256-bit intructions. The longBruno Cardoso Lopes
term goal here is to be able to match enough of vector_shuffle and build_vector so all avx intrinsics which aren't mapped to their own built-ins but to shufflevector calls can be codegen'd. This is the first (baby) step, support building zeroed vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .tdJohnny Chen
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2. Recover by looking for ARM:USAT encoding pattern before delegating to the auto- gened decoder. Added a "usat" test case to arm-tests.txt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110894 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12MC/X86/AsmParser: Give an explicit error message when we reject an instructionDaniel Dunbar
because it could have an ambiguous suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110890 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12MC/AsmParser: Push the burdon of emitting diagnostics about unmatchedDaniel Dunbar
instructions onto the target specific parser, which can do a better job. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110889 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl',Daniel Dunbar
target specific parsers can adapt the TargetAsmParser to this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110888 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.Johnny Chen
Added two test cases to arm-tests.txt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110880 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Even if a variable has constant value all the time, it is still a variable ↵Devang Patel
in gdb's eyes. Tested by scope.exp in gdb testsuite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Move the ARM SSAT and USAT optional shift amount operand out of theBob Wilson
instruction opcode. This also fixes part of PR7792. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Fix <rdar://problem/8282498> even if it doesn't reproduce on trunk.Jakob Stoklund Olesen
When a register is defined by a partial load: %reg1234:sub_32 = MOV32mr <fi#-1>; GR64:%reg1234 That load cannot be folded into an instruction using the full 64-bit register. It would become a 64-bit load. This is related to the recent change to have isLoadFromStackSlot return false on a sub-register load. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110874 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Fix a subtle use-after-free issue.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110863 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Clean up ConstantRange a bit:Nick Lewycky
- remove ashr which never worked. - fix lshr and shl and add tests. - remove dead function "intersect1Wrapped". - add a new sub method to subtract ranges, with test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110861 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Make LoopPass::getContainedPass return a LoopPass* instead of a Pass*Dan Gohman
and remove casts from all its callers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110848 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Remove BasicBlockPass::runOnFunction, which was unused.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110847 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Delete FunctionPass::run, which is unused.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110843 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Delete FunctionPass::runOnModule, which is unused.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Don't use unsigned char for alignments in TargetData. There aren'tDan Gohman
that many of these things, so the memory savings isn't significant, and there are now situations where there can be alignments greater than 128. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110836 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Use ISD::ADD instead of ISD::SUB with a negated constant. ThisDan Gohman
avoids trouble if the return type of TD->getPointerSize() is changed to something which doesn't promote to a signed type, and is simpler anyway. Also, use getCopyFromReg instead of getRegister to read a physical register's value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110835 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Fix a FIXME. The SlotIndex::Slot enum should be private.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110826 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11cortex m4 has floating point support, but only single precision.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110810 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Consider this code snippet:Bill Wendling
float t1(int argc) { return (argc == 1123) ? 1.234f : 2.38213f; } We would generate truly awful code on ARM (those with a weak stomach should look away): _t1: movw r1, #1123 movs r2, #1 movs r3, #0 cmp r0, r1 mov.w r0, #0 it eq moveq r0, r2 movs r1, #4 cmp r0, #0 it ne movne r3, r1 adr r0, #LCPI1_0 ldr r0, [r0, r3] bx lr The problem was that legalization was creating a cascade of SELECT_CC nodes, for for the comparison of "argc == 1123" which was fed into a SELECT node for the ?: statement which was itself converted to a SELECT_CC node. This is because the ARM back-end doesn't have custom lowering for SELECT nodes, so it used the default "Expand". I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this testcase, but can obviously be expanded to include more cases. Now we generate this, which looks optimal to me: _t1: movw r1, #1123 movs r2, #0 cmp r0, r1 adr r0, #LCPI0_0 it eq moveq r2, #4 ldr r0, [r0, r2] bx lr .align 2 LCPI0_0: .long 1075344593 @ float 2.382130e+00 .long 1067316150 @ float 1.234000e+00 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110799 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Report error if codegen tries to instantiate a ARM target when the cpu does ↵Evan Cheng
support it. e.g. cortex-m* processors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11ArchV7M implies HW division instructions.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110797 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11ArchV6T2, V7A, and V7M implies Thumb2; Archv7A implies NEON.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110796 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.)Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110795 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11MC/ARM: Add basic support for handling predication by parsing it out of the ↵Daniel Dunbar
mnemonic into a separate operand form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11MC/ARM: Split mnemonic on '.' characters.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110793 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11MC/ARM: Fill in ARMOperand::dump a bit.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110792 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11llvm-mc: Add -show-inst-operands, for dumping the parsed instruction ↵Daniel Dunbar
representation before matching. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110791 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11MCAsmParser: Add dump() hook to MCParsedAsmOperand.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110790 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11MC/ARM: Add an ARMOperand class for condition codes.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110788 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Really control isel of barrier instructions with cpu feature.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110787 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bitEvan Cheng
instructions: dmb, dsb, isb, msr, and mrs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110786 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11- Add subtarget feature -mattr=+db which determine whether an ARM cpu has theEvan Cheng
memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11MC/ARM: Switch to using the generated match functions instead of stub ↵Daniel Dunbar
implementations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110783 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11MC/ARM: Enable generation of the ARM asm matcher, not that it can do much.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110782 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11ARM: Mark some disassembler only instructions as not available for matching --Daniel Dunbar
for some reason they have a very odd MCInst form where the operands overlap, but I haven't dug in to find out why yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110781 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11ARM: Quote $p in an asm string.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110780 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Improve indentation.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110778 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110762 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Mark ARM compare instructions as isCompare.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11When analyzing loop exit conditions combined with and and or, don'tDan Gohman
make any assumptions about when the two conditions will agree on when to permit the loop to exit. This fixes PR7845. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110758 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Add a separate ARM instruction format for Saturate instructions.Bob Wilson
(I discovered 2 more copies of the ARM instruction format list, bringing the total to 4!! Two of them were already out of sync. I haven't yet gotten into the disassembler enough to know the best way to fix this, but something needs to be done.) Add support for encoding these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Rename and reorder the arguments to isImpliedCond, for consistency and clarity.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110750 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10CBZ and CBNZ are implemented.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Add AVX matching patterns to Packed Bit Test intrinsics.Bruno Cardoso Lopes
Apply the same approach of SSE4.1 ptest intrinsics but create a new x86 node "testp" since AVX introduces vtest{ps}{pd} instructions which set ZF and CF depending on sign bit AND and ANDN of packed floating-point sources. This is slightly different from what the "ptest" does. Tests comming with the other 256 intrinsics tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110744 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Now that we're using ConstantRange to represent potential values, make use ↵Owen Anderson
of that represenation to create constraints from comparisons other than eq/neq. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110742 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Add the minimal amount of smarts necessary to instcombine of shufflevectors ↵Nate Begeman
to recognize patterns generated by clang for transpose of a matrix in generic vectors. This is made of two parts: 1) Propagating vector extracts of hi/lo half into their users 2) Recognizing an insertion of even elements followed by the odd elements as an unpack. Testcase to come, but this shrinks the # of shuffle instructions generated on x86 from ~40 to the minimal 8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110734 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Turn optimize compares back on with fix. We needed to test that a machine op wasBill Wendling
a register before checking if it was defined. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110733 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Give up on register class recalculation when the register is used with subregJakob Stoklund Olesen
operands. We don't currently have a hook to provide "the largest super class of A where all registers' getSubReg(subidx) is valid and in B". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110730 91177308-0d34-0410-b5e6-96231b3b80d8
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