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2013-05-01Hexagon: Clear isKill flag on the predicate register inJyotsna Verma
PredicateInstruction function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180884 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-01This patch breaks up Wrap.h so that it does not have to include all of Filip Pizlo
the things, and renames it to CBindingWrapping.h. I also moved CBindingWrapping.h into Support/. This new file just contains the macros for defining different wrap/unwrap methods. The calls to those macros, as well as any custom wrap/unwrap definitions (like for array of Values for example), are put into corresponding C++ headers. Doing this required some #include surgery, since some .cpp files relied on the fact that including Wrap.h implicitly caused the inclusion of a bunch of other things. This also now means that the C++ headers will include their corresponding C API headers; for example Value.h must include llvm-c/Core.h. I think this is harmless, since the C API headers contain just external function declarations and some C types, so I don't believe there should be any nasty dependency issues here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180881 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-01SROA: Generate selects instead of shuffles when blending values because this ↵Nadav Rotem
is the cannonical form. Shuffles are more difficult to lower and we usually don't touch them, while we do optimize selects more often. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180875 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-01[inline asm] Return an undef SDValue of the expected value type, rather thanChad Rosier
report a fatal error. This allows us to continue processing the translation unit. Test case to come on the clang side because we need an inline asm diagnostics handler in place. rdar://13446483 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180873 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-01Optimize away nop CONCAT_VECTOR nodes.Nadav Rotem
Optimize CONCAT_VECTOR nodes that merge EXTRACT_SUBVECTOR values that extract from the same vector. rdar://13402653 PR15866 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180871 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-01Copy LLVM bitcode reader to generate a PNaCl wire format reader.Karl Schimpf
Copy classes for LLVM BitcodeReader into a NaCl subdirectory, to create a wire format version. Renames classes/functions to include NaCl prefix, so that they don't conflict with the LLVM Bitcode reader. Also implements pnacl-thaw, showing that we can read the PNaCl wire format files. BUG= https://code.google.com/p/nativeclient/issues/detail?id=3405 R=jvoung@chromium.org Review URL: https://codereview.chromium.org/14314016
2013-05-01Now that the underlying issue is fixed, revert r180750 and r180722.Rafael Espindola
The cause of the windows failures was fixed by r180791. Revert to the state after Sabre's original revert. Original message: revert r179735, it has no testcases, and doesn't really make sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180844 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-01Put VMOVPQIto64rr in the VRPDI class.Rafael Espindola
Patch by Joshua Magee. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180842 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-01Fixes a buffer overrun where the allocated buffer wasn't large enough to ↵Aaron Ballman
accommodate the closing quote escape rules in some instances. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180836 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-01Revert "InstCombine: Fold more shuffles of shuffles."Jim Grosbach
This reverts commit r180802 There's ongoing discussion about whether this is the right place to make this transformation. Reverting for now while we figure it out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180834 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30[mips] Fix handling of instructions which copy to/from accumulator registers.Akira Hatanaka
Expand copy instructions between two accumulator registers before callee-saved scan is done. Handle copies between integer GPR and hi/lo registers in MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180827 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30Only pass 'returned' to target-specific lowering code when the value of ↵Stephen Lin
entire register is guaranteed to be preserved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180825 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30Fix a use after free. RI is freed before the call to getDebugLoc(). ToRichard Trieu
prevent this, capture the location before RI is freed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180824 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30[mips] Instruction selection patterns for DSP-ASE vector select and compareAkira Hatanaka
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180820 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30Temporarily revert "Change the informal convention of DBG_VALUE so that we ↵Adrian Prantl
can express a" because it breaks some buildbots. This reverts commit 180816. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180819 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30Change the informal convention of DBG_VALUE so that we can express aAdrian Prantl
register-indirect address with an offset of 0. It used to be that a DBG_VALUE is a register-indirect value if the offset (operand 1) is nonzero. The new convention is that a DBG_VALUE is register-indirect if the first operand is a register and the second operand is an immediate. For plain registers use the combination reg, reg. rdar://problem/13658587 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180816 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30MI Sched: revert a minor heuristic that snuck in with -misched-vcopy.Andrew Trick
I'll fix the heuristic in a general way in a follow-up commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180815 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30[mips] Simplify code.Akira Hatanaka
No intended functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180807 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30Fix a typoNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180806 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30InstCombine: Fold more shuffles of shuffles.Jim Grosbach
Always fold a shuffle-of-shuffle into a single shuffle when there's only one input vector in the first place. Continue to be more conservative when there's multiple inputs. rdar://13402653 PR15866 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180802 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30[mips] Clear isCommutable bit of instructions which are not commutable.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180801 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30LocalStackSlotAllocation improvementsHal Finkel
First, taking advantage of the fact that the virtual base registers are allocated in order of the local frame offsets, remove the quadratic register-searching behavior. Because of the ordering, we only need to check the last virtual base register created. Second, store the frame index in the FrameRef structure, and get the frame index and the local offset from this structure at the top of the loop iteration. This allows us to de-nest the loops in insertFrameReferenceRegisters (and I think makes the code cleaner). I also moved the needsFrameBaseReg check into the first loop over instructions so that we don't bother pushing FrameRefs for instructions that don't want a virtual base register anyway. Lastly, and this is the only functionality change, avoid the creation of single-use virtual base registers. These are currently not useful because, in general, they end up replacing what would be one r+r instruction with an add and a r+i instruction. Committing this removes the XFAIL in CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll Jim has okayed this off-list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180799 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30Text files should not be marked executable.Rafael Espindola
Patch by Oliver Pinter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180797 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30Spelling. Thanks, Eric.Adrian Prantl
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180794 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30Set debug locations for branch instructions created during inlining, evenAdrian Prantl
the inlined function has multiple returns. rdar://problem/12415623 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180793 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30Change getSlotIndex to return unsigned.Rafael Espindola
The actual storage was already using unsigned, but the interface was using uint64_t. This is wasteful on 32 bits and looks to be the root causes of a miscompilation on Windows where a value was being sign extended to 64bits to compare with the result of getSlotIndex. Patch by Pasi Parviainen! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180791 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30Fix Addend computation for non external relocations on Macho.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180790 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30Fix a bug in foldSelectICmpAndOr.David Majnemer
Differences in bitwidth between X and Y could exist even if C1 and C2 have the same Log2 representation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180779 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30s tightens up the encoding description for ARM post-indexed ldr ↵Mihai Popa
instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180778 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30Fix "Combine bit test + conditional or into simple math"David Majnemer
This fixes the optimization introduced in r179748 and reverted in r179750. While the optimization was sound, it did not properly respect differences in bit-width. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180777 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30Refactoring patch.Stepan Dyatkovskiy
1. VarArgStyleRegisters: functionality that emits "store" instructions for byval regs moved out into separated method "StoreByValRegs". Before this patch VarArgStyleRegisters had confused use-cases. It was used for both variadic functions and for regular functions with byval parameters. In last case it created new stack-frame and registered it as VarArg frame, that is wrong. This patch replaces VarArgsStyleRegisters usage for byval parameters with StoreByValRegs method. 2. In ARMMachineFunctionInfo, "get/setVarArgsRegSaveSize" was renamed to "get/setArgRegsSaveSize". By the same reason. Sometimes it was used for variadic functions, and sometimes for byval parameters in regular functions. Actually, this property means the size of registers, that keeps arguments, and thats why it was renamed. 3. In ARMISelLowering.cpp, ARMTargetLowering class, in methods computeRegArea and StoreByValRegs, VARegXXXXXX was renamed to ArgRegsXXXXXX still by the same reasons. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180774 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30Collect the Addend for external relocs.Rafael Espindola
This fixes 2013-04-04-RelocAddend.ll. We don't have a testcase for non external relocs with an Addend. I will try to write one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180767 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: Always use texture cache for compute shadersVincent Lejeune
This will improve the performance of memory reads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180762 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: use native for aluVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180761 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: Packetize instructionsVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180760 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chipsVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: Add a Bank Swizzle operandVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180758 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: Take inner dependency into tex/vtx clausesVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180757 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: Turn TEX/VTX into native instructionsVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180756 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: Add FetchInst bit to instruction defs to denote vertex/tex instructionsVincent Lejeune
v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: Add some new processor variantsVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180753 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: Clean up instruction class definitionsVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180752 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30R600: config section now reports use of killgtVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180751 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29Revert the command line option patch. However, keep the part that makes this ↵Bill Wendling
pass on Windows. I.e., we don't emit the target dependent attributes in a comment before the function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180750 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29Use unique'ed types for varargs expansion instead of non-unique named types.Jan Voung
Saves a tiny bit of space for var-args heavy bitcode programs, since the anonymous types get unique'ed. E.g., saves 20KB out of 1.6MB in spec gcc when comparing the gzipped files, or about 100KB when not zipped. This is only a savings with the current wire format. If we change the alloca, etc. to only have sizes and not struct types then we would also not have this duplication. Just happened to notice while looking through code for what struct types remain used in the bitcode. random cleanup for: BUG= https://code.google.com/p/nativeclient/issues/detail?id=3338 R=mseaborn@chromium.org Review URL: https://codereview.chromium.org/14197004
2013-04-29Emit the TLS initialization function pointers into the correct section.Bill Wendling
The `llvm.tls_init_funcs' (created by the front-end) holds pointers to the TLS initialization functions. These need to be placed into the correct section so that they are run before `main()'. <rdar://problem/13733006> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180737 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29Add getSymbolAlignment to the ObjectFile interface.Rafael Espindola
For regular object files this is only meaningful for common symbols. An object file format with direct support for atoms should be able to provide alignment information for all symbols. This replaces getCommonSymbolAlignment and fixes test-common-symbols-alignment.ll on darwin. This also includes a fix to MachOObjectFile::getSymbolFlags. It was marking undefined symbols as common (already tested by existing mcjit tests now that it is used). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180736 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29R600: Use correct CF_END instruction on Northern Island GPUsTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180735 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29R600: Fix encoding of CF_END_{EG, R600} instructionsTom Stellard
The EOP bit was not being encoded. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180734 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29Rationalize what is public in RuntimeDyldMachO and RuntimeDyldELF.Rafael Espindola
The implemented RuntimeDyldImpl interface is public. Everything else is private. Since these classes are not inherited from (yet), there is no need to have protected members. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180733 91177308-0d34-0410-b5e6-96231b3b80d8
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