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2013-07-17Disallow a global address in the x86-64 displacement field.Jim Stichnoth
This applies only to %r15 sandboxed memory references. The problem is that if the index register is negative, the sandboxing operation will cause the index to become a large positive 32-bit value, which combined with the displacement, will overflow and try to reference memory outside the sandbox. This situation may legitimately occur if the compiler happens to construct a (constant) interior pointer to the middle of the global struct/array, and then dereferences it with a variable offset. After this fix, pnacl/scripts/testsuite_known_failures_pnacl.txt can be updated to remove the "aha x86-64" known failure. BUG= https://code.google.com/p/nativeclient/issues/detail?id=3517 R=eliben@chromium.org Review URL: https://codereview.chromium.org/17987002
2013-07-16More tests passEli Bendersky
2013-07-16Fixing make check errors...Eli Bendersky
2013-07-16Make it compileEli Bendersky
2013-07-15Trying to get the thing to copmile...Eli Bendersky
2013-07-15Merge commit '7dfcb84fc16b3bf6b2379713b53090757f0a45f9'Eli Bendersky
Conflicts: docs/LangRef.rst include/llvm/CodeGen/CallingConvLower.h include/llvm/IRReader/IRReader.h include/llvm/Target/TargetMachine.h lib/CodeGen/CallingConvLower.cpp lib/IRReader/IRReader.cpp lib/IRReader/LLVMBuild.txt lib/IRReader/Makefile lib/LLVMBuild.txt lib/Makefile lib/Support/MemoryBuffer.cpp lib/Support/Unix/PathV2.inc lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMTargetMachine.cpp lib/Target/Mips/CMakeLists.txt lib/Target/Mips/MipsDelaySlotFiller.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsSubtarget.cpp lib/Target/Mips/MipsSubtarget.h lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrControl.td lib/Target/X86/X86InstrFormats.td lib/Transforms/IPO/ExtractGV.cpp lib/Transforms/InstCombine/InstCombineCompares.cpp lib/Transforms/Utils/SimplifyLibCalls.cpp test/CodeGen/X86/fast-isel-divrem.ll test/MC/ARM/data-in-code.ll tools/Makefile tools/llvm-extract/llvm-extract.cpp tools/llvm-link/CMakeLists.txt tools/opt/CMakeLists.txt tools/opt/LLVMBuild.txt tools/opt/Makefile tools/opt/opt.cpp
2013-07-11Fix ARM paired GPR COPY loweringJF Bastien
ARM paired GPR COPY was being lowered to two MOVr without CC. This patch puts the CC back. I sent this patch upstream (with a test) but haven't received a review yet. This seems like a simple oversight in the code, and is holding my atomics patch so I'd like to get it into our repo. R=dschuff@chromium.org TEST= ./scons run_llvm_bitmanip_intrinsics_test platform=arm BUG= no CC on MOVr Review URL: https://codereview.chromium.org/18047006
2013-07-11Sandbox ARM load/store exclusive dualJF Bastien
PNaCl's LLVM sandboxing wasn't correct for ARM load/store exclusive dual. I encountered this while running our testsuite with my atomic changes: the tests which use volatile 64-bit values started failing validation. R=dschuff@chromium.org BUG= validation failure TEST= ./pnacl/test.sh test-arm Review URL: https://codereview.chromium.org/18978015
2013-07-10Fix ARM LDMIA MI.JF Bastien
The instruction that was generated for paired register stack slot load was wrong. This was fixed by Tim Northover in LLVM 3.3 commit 179977, but his patch does much more and doesn't apply as-is to our tree. I'll therefore punt applying the full patch to when we rebase to 3.3. I encountered the issue while working on atomics (64-bit atomics require paired registers on ARM), and saw the 3.3 fix when I tried upstreaming my fix. BUG= non TEST= ./pnacl/test.sh test-arm R=eliben@chromium.org Review URL: https://codereview.chromium.org/18699004
2013-07-09PNaCl: Fix negative relocation addends on x86-32Mark Seaborn
Disable an assertion. This assertion made the behaviour on x86-32 inconsistent with x86-64 and ARM. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3548 TEST=*.ll tests + PNaCl toolchain trybots Review URL: https://codereview.chromium.org/18261008
2013-07-08R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst regTom Stellard
Patch by: Vincent Lejeune https://bugs.freedesktop.org/show_bug.cgi?id=64877 NOTE: This is a candidate for the 3.3 branch. Merged from r182600 Author: Tom Stellard <thomas.stellard@amd.com> Date: Thu May 23 18:26:42 2013 +0000 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@185868 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25Revert "Apply upstream r183551, r183601, r183624 and r183794"Jan Voung
Revert this until we fix i1 sext. Currently, it uses LSL and ASR, which are pseudo-instructions and get dropped on the floor when generating .o files. We'll fix that, but for now revert to green the bots. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3501 R=jfb@chromium.org Review URL: https://codereview.chromium.org/17715002
2013-06-24Merge r179774: Allow misaligned stores in x86 fast-isel.Mark Seaborn
This change will fix the regression in -O0 translation time caused by putting "align 1" on integer loads and stores, which was causing FastISel to fall back to SelectionDAG more often. > In X86FastISel::X86SelectStore(), improperly aligned stores are > rejected and handled by the DAG-based ISel. However, > X86FastISel::X86SelectLoad() makes no such requirement. There > doesn't appear to be an x86 architectural correctness issue with > allowing potentially unaligned store instructions. This patch > removes this restriction. > > Patch by Jim Stichnot. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3445 TEST=PNaCl toolchain trybots Review URL: https://codereview.chromium.org/17575003
2013-06-19Fix an x86-64 fast-isel address calculation overflow.Jim Stichnoth
Disallow large displacements in NaCl addressing modes, by rejecting the fast-isel selection and using the logic in the DAG-based isel. BUG= https://code.google.com/p/nativeclient/issues/detail?id=3502 R=dschuff@chromium.org Review URL: https://codereview.chromium.org/16959013
2013-06-17PNaCl: Turn on ABI verifier by default in sandboxed translatorMark Seaborn
Change pnacl-llc.cpp to enable the verifier. This causes two problems which we fix: * The ABI check for declared-but-not-defined functions fails in streaming mode. Fixing this would involve changing the bitcode reader. For now, disable this check when in streaming mode. Add a flag to PNaClABIVerifyModule. * ARM's GlobalMerge pass modifies functions' global variable references to use ConstantExprs that the ABI checker rejects. Address this by disabling GlobalMerge for now. GlobalMerge does not provide much benefit at the moment anyway, because, with the FlattenGlobals pass applied, GlobalMerge doesn't merge variables with alignment >1. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3465 TEST=PNaCl toolchain trybots Review URL: https://codereview.chromium.org/17190002
2013-06-13Fix PrologEpilogInserter to save and restore all callee saved registersDerek Schuff
if the function calls _builtin_unwind_init() Also fix the list of callee-saved registers returned by X86RegisterInfo::getCalleeSavedRegisters BUG= https://code.google.com/p/nativeclient/issues/detail?id=3486 R=mseaborn@chromium.org Review URL: https://codereview.chromium.org/16987002
2013-06-11Apply upstream r183551, r183601, r183624 and r183794JF Bastien
Rename countTrailingZeros to the older CountTrailingZeros_32, mark as localmod. These patches fix correctness issues with ARM FastISel, and should make it faster while generating better code. BUG= none TEST= self R=jvoung@chromium.org Review URL: https://codereview.chromium.org/16712002
2013-06-04Merging r183108:Bill Wendling
------------------------------------------------------------------------ r183108 | vljn | 2013-06-03 08:44:42 -0700 (Mon, 03 Jun 2013) | 1 line R600: CALL_FS consumes a stack size entry ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@183181 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-31Apply LLVM upstream: r182877 - Enable FastISel on ARM for Linux and NaClJF Bastien
This also pulls in a TargetMachine.h change from r176986 and changes NaCl's intrinsics-bitmanip.ll test to account for register spills at O0. FastISel was only enabled for iOS ARM and Thumb2, this patch enables it for ARM (not Thumb2) on Linux and NaCl. Thumb2 support needs a bit more work, mainly around register class restrictions. The patch punts to SelectionDAG when doing TLS relocation on non-Darwin targets. I will fix this and other FastISel-to-SelectionDAG failures in a separate patch. The patch also forces FastISel to retain frame pointers: iOS always keeps them for backtracking (so emitted code won't change because of this), but Linux was getting much worse code that was incorrect when using big frames (such as test-suite's lencod). I'll also fix this in a later patch, it will probably require a peephole so that FastISel doesn't rematerialize frame pointers back-to-back. The test changes are straightforward, similar to: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html They also add a vararg test that got dropped in that change. I ran all of test-suite on A15 hardware with --optimize-option=-O0 and all the tests pass. R=dschuff@chromium.org, jvoung@chromium.org BUG= https://code.google.com/p/nativeclient/issues/detail?id=3120 Review URL: https://codereview.chromium.org/15671004
2013-05-29Apply LLVM upstream: r182175 - Support unaligned load/store on more ARM targetsJF Bastien
This patch matches GCC behavior: the code used to only allow unaligned load/store on ARM for v6+ Darwin, it will now allow unaligned load/store for v6+ Darwin as well as for v7+ on Linux and NaCl. The distinction is made because v6 doesn't guarantee support (but LLVM assumes that Apple controls hardware+kernel and therefore have conformant v6 CPUs), whereas v7 does provide this guarantee (and Linux/NaCl behave sanely). The patch keeps the -arm-strict-align command line option, and adds -arm-no-strict-align. They behave similarly to GCC's -mstrict-align and -mnostrict-align. I originally encountered this discrepancy in FastIsel tests which expect unaligned load/store generation. Overall this should slightly improve performance in most cases because of reduced I$ pressure. R=dschuff@chromium.org Review URL: https://codereview.chromium.org/15677005
2013-05-29Merging r182585:Bill Wendling
------------------------------------------------------------------------ r182585 | aaronballman | 2013-05-23 07:55:00 -0700 (Thu, 23 May 2013) | 1 line Setting the default value (fixes CRT assertions about uninitialized variable use when doing debug MSVC builds), and fixing coding style. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182830 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-29Merging r182394:Bill Wendling
------------------------------------------------------------------------ r182394 | jholewinski | 2013-05-21 09:51:30 -0700 (Tue, 21 May 2013) | 1 line [NVPTX] Add @llvm.nvvm.sqrt.f() intrinsic ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182829 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-29Merging r182298:Bill Wendling
------------------------------------------------------------------------ r182298 | jholewinski | 2013-05-20 09:42:18 -0700 (Mon, 20 May 2013) | 1 line [NVPTX] Fix mis-use of CurrentFnSym in NVPTXAsmPrinter. This was causing a symbol name error in the output PTX. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182828 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-29Merging r182297:Bill Wendling
------------------------------------------------------------------------ r182297 | jholewinski | 2013-05-20 09:42:16 -0700 (Mon, 20 May 2013) | 1 line [NVPTX] Add programmatic interface to NVVMReflect pass ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182827 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-29Merging r182254:Bill Wendling
------------------------------------------------------------------------ r182254 | jholewinski | 2013-05-20 05:13:32 -0700 (Mon, 20 May 2013) | 12 lines [NVPTX] Add GenericToNVVM IR converter to better handle idiomatic LLVM IR inputs This converter currently only handles global variables in address space 0. For these variables, they are promoted to address space 1 (global memory), and all uses are updated to point to the result of a cvta.global instruction on the new variable. The motivation for this is address space 0 global variables are illegal since we cannot declare variables in the generic address space. Instead, we place the variables in address space 1 and explicitly convert the pointer to address space 0. This is primarily intended to help new users who expect to be able to place global variables in the default address space. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182826 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-29Merging r182253:Bill Wendling
------------------------------------------------------------------------ r182253 | jholewinski | 2013-05-20 05:13:28 -0700 (Mon, 20 May 2013) | 1 line [NVPTX] Fix i1 kernel parameters and global variables. ABI rules say we need to use .u8 for i1 parameters for kernels. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182825 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22Merging r182486:Bill Wendling
------------------------------------------------------------------------ r182486 | d0k | 2013-05-22 10:01:12 -0700 (Wed, 22 May 2013) | 3 lines X86: When expanding PCMPGTQ to PCMPGTD we always want to compare the lower halves as unsigned. Take #2 on fixing PR15977. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182489 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21Merging r182385:Bill Wendling
------------------------------------------------------------------------ r182385 | hfinkel | 2013-05-21 07:21:09 -0700 (Tue, 21 May 2013) | 9 lines Fix PPC branch selection for counter-based branches Although I had added some support for the BDZ/BDNZ branches into the selector (in r158204), I had not correctly adjusted the condition at the top of the loop. As a result, these branches were still essentially unsupported. This fixes PR16086. Unfortunately, any test case would be very large (because it would need to force the loop backedge to exceed the range of the 16-bit immediate). ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182431 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21Merging r182112:Bill Wendling
------------------------------------------------------------------------ r182112 | tstellar | 2013-05-17 08:23:12 -0700 (Fri, 17 May 2013) | 1 line R600: Pass MCSubtargetInfo reference to R600CodeEmitter ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182416 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21Merging r182364:Bill Wendling
------------------------------------------------------------------------ r182364 | d0k | 2013-05-21 02:58:54 -0700 (Tue, 21 May 2013) | 4 lines X86: When emulating unsigned PCMPGTQ with PCMPGTD, fix the sign bit for the smaller type. Otherwise we'll get a mix of signed and unsigned compares. Fixes PR15977. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17Merging r182113:Bill Wendling
------------------------------------------------------------------------ r182113 | tstellar | 2013-05-17 08:23:21 -0700 (Fri, 17 May 2013) | 9 lines R600: Fix encoding for R600 family GPUs Reviewed-by: Vincent Lejeune <vljn@ovi.com> https://bugs.freedesktop.org/show_bug.cgi?id=64193 https://bugs.freedesktop.org/show_bug.cgi?id=64257 https://bugs.freedesktop.org/show_bug.cgi?id=64320 NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182174 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17Re-allow an x86-32 fast-isel optimization for NaCl / use shorter insts.Jan Voung
There was an old fix for r+r based memory references on x86-64 that checked for isTargetNaCl() instead of isTargetNaCl64(). This disabled some r+r for 32-bit. However, fast isel only sets up r+r with geps, and we don't have geps in the stable ABI. We could potentially add some similar pattern matching in the future... The problem we *do* see with the current bitcode, is that this change also made it preferred to use an index register instead of a base register. This made the memory references on x86-32 look like: cmpl ..., (,%eax,1) instead of cmpl ..., (%eax) So we had longer instructions. Total zipped nexe sizes: 5.73MB (old) vs 5.59 MB (new) (2.5%) Total not zipped: 17.28MB vs 16.28 MB (6%) runtime diffs (min of 5 runs) * eon 4.94 (old) vs 4.72 (new) (~4%) * mesa 21.64 vs 21.08 * mcf 5.76 vs 5.60 * vortex 4.21 vs 4.05 * perlbmk 27.62 vs 26.55 (the rest were under 2% better) BUG=https://code.google.com/p/nativeclient/issues/detail?id=3359 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/15047013
2013-05-17Merging r181706:Bill Wendling
------------------------------------------------------------------------ r181706 | rafael | 2013-05-13 07:34:48 -0700 (Mon, 13 May 2013) | 1 line Remove unused fields and arguments. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182147 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181529:Bill Wendling
------------------------------------------------------------------------ r181529 | void | 2013-05-09 11:21:45 -0700 (Thu, 09 May 2013) | 8 lines Simplify the code a bit. The compact unwind registers were defined in two different places. It's better just to place them in the function that uses them and specify that this is a 64-bit or 32-bit machine. No functionality change. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181956 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181540:Bill Wendling
------------------------------------------------------------------------ r181540 | void | 2013-05-09 13:10:38 -0700 (Thu, 09 May 2013) | 11 lines Generate a compact unwind encoding in the face of a stack alignment push. We generate a `push' of a random register (%rax) if the stack needs to be aligned by the size of that register. However, this could mess up compact unwind generation. In particular, we want to still generate compact unwind in the presence of this monstrosity. Check if the push of of the %rax/%eax register. If it is and it's marked with the `FrameSetup' flag, then we can generate a compact unwind encoding for the function only if the push is the last FrameSetup instruction. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181955 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181580:Bill Wendling
------------------------------------------------------------------------ r181580 | tstellar | 2013-05-09 19:09:45 -0700 (Thu, 09 May 2013) | 10 lines R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns The BFE optimization was the only one we were actually using, and it was emitting an intrinsic that we don't support. https://bugs.freedesktop.org/show_bug.cgi?id=64201 Reviewed-by: Christian König <christian.koenig@amd.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181954 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181579:Bill Wendling
------------------------------------------------------------------------ r181579 | tstellar | 2013-05-09 19:09:39 -0700 (Thu, 09 May 2013) | 8 lines R600: Expand SUB for v2i32/v4i32 Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181953 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181578:Bill Wendling
------------------------------------------------------------------------ r181578 | tstellar | 2013-05-09 19:09:34 -0700 (Thu, 09 May 2013) | 10 lines R600: Expand MUL for v4i32/v2i32 Fixes piglit test for OpenCL builtin mul24, and allows mad24 to run. Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181952 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181577:Bill Wendling
------------------------------------------------------------------------ r181577 | tstellar | 2013-05-09 19:09:29 -0700 (Thu, 09 May 2013) | 10 lines R600: Expand SRA for v4i32/v2i32 v2: Add v4i32 test Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181951 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181576:Bill Wendling
------------------------------------------------------------------------ r181576 | tstellar | 2013-05-09 19:09:24 -0700 (Thu, 09 May 2013) | 10 lines R600: Expand vselect for v4i32 and v2i32 v2: Add vselect v4i32 test Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181950 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16Merging r181792:Bill Wendling
------------------------------------------------------------------------ r181792 | tstellar | 2013-05-14 07:42:56 -0700 (Tue, 14 May 2013) | 8 lines R600/SI: Add processor type for Hainan asic Patch by: Alex Deucher Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181949 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-15Merging r181842:Bill Wendling
------------------------------------------------------------------------ r181842 | arnolds | 2013-05-14 15:33:24 -0700 (Tue, 14 May 2013) | 14 lines ARM ISel: Don't create illegal types during LowerMUL The transformation happening here is that we want to turn a "mul(ext(X), ext(X))" into a "vmull(X, X)", stripping off the extension. We have to make sure that X still has a valid vector type - possibly recreate an extension to a smaller type. In case of a extload of a memory type smaller than 64 bit we used create a ext(load()). The problem with doing this - instead of recreating an extload - is that an illegal type is exposed. This patch fixes this by creating extloads instead of ext(load()) sequences. Fixes PR15970. radar://13871383 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181946 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14Merging r181450:Bill Wendling
------------------------------------------------------------------------ r181450 | uweigand | 2013-05-08 10:50:07 -0700 (Wed, 08 May 2013) | 16 lines [PowerPC] Fix regression in generating @ha/@l relocs The patch I committed as revision 167864 introduced a regression that causes LLVM to no longer generate appropriate relocs for @ha/@l symbol references (but fail an assertion instead). This is fixed here by re-enabling support for the VK_PPC_GAS_HA16/ VK_PPC_GAS_LO16 variant kinds (and their Darwin variants) in PPCELFObjectWriter.cpp. Tested by running projects/test-suite in -m32 mode with the integrated assembler forced on. A standalone test case will be committed shortly as well. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181816 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-14Merging r181800:Bill Wendling
------------------------------------------------------------------------ r181800 | wschmidt | 2013-05-14 09:08:32 -0700 (Tue, 14 May 2013) | 15 lines PPC32: Fix stack collision between FP and CR save areas. The changes to CR spill handling missed a case for 32-bit PowerPC. The code in PPCFrameLowering::processFunctionBeforeFrameFinalized() checks whether CR spill has occurred using a flag in the function info. This flag is only set by storeRegToStackSlot and loadRegFromStackSlot. spillCalleeSavedRegisters does not call storeRegToStackSlot, but instead produces MI directly. Thus we don't see the CR is spilled when assigning frame offsets, and the CR spill ends up colliding with some other location (generally the FP slot). This patch sets the flag in spillCalleeSavedRegisters for PPC32 so that the CR spill is properly detected and gets its own slot in the stack frame. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181815 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10LLVM: Add ELF Note section to NaCl object files identifying them as such to goldDerek Schuff
This is needed to switch the native linker to one based on upstream binutils 2.23 R=mseaborn@chromium.org BUG= https://code.google.com/p/nativeclient/issues/detail?id=2971 also related to bug https://code.google.com/p/nativeclient/issues/detail?id=3424 Review URL: https://codereview.chromium.org/15067009
2013-05-09Merging r181423:Bill Wendling
------------------------------------------------------------------------ r181423 | hfinkel | 2013-05-08 05:16:14 -0700 (Wed, 08 May 2013) | 5 lines PPCInstrInfo::optimizeCompareInstr should not optimize FP compares The floating-point record forms on PPC don't set the condition register bits based on a comparison with zero (like the integer record forms do), but rather based on the exception status bits. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181507 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08Add dependency on NaClTransforms to lib/Target/ARM.Jan Voung
It depends on NaClTransforms for the denominator zero checks transform. BUG=https://code.google.com/p/nativeclient/issues/detail?id=2833 (fix build) R=dschuff@chromium.org Review URL: https://codereview.chromium.org/15067004
2013-05-08Insert denominator zero checks for NaClDavid Sehr
This IR pass for ARM inserts a comparison and a branch to trap if the denominator of a DIV or REM instruction is zero. This makes ARM fault identically to x86 in this case. BUG= https://code.google.com/p/nativeclient/issues/detail?id=2833 R=eliben@chromium.org Review URL: https://codereview.chromium.org/14607004
2013-05-08Merge of r181312Richard Sandiford
[SystemZ] Fix InitMCCodeGenInfo call createSystemZMCCodeGenInfo was not passing the optimization level to InitMCCodeGenInfo(), so -O0 would be ignored. Fixes DebugInfo/namespace.ll after the changes in r181271. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181419 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08Merging r181313:Bill Wendling
------------------------------------------------------------------------ r181313 | mkuper | 2013-05-07 07:05:33 -0700 (Tue, 07 May 2013) | 1 line Re-enable AVX detection on x64 platforms. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@181399 91177308-0d34-0410-b5e6-96231b3b80d8
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