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When built as nexe, llc is configured and built for one arch only.
Variables FlagSfiData, FlagSfiLoad, FlagSfiStore, FlagSfiStack, and
FlagSfiBranch have to availabe for MIPS as well, so this change moves
them from ARM-only code to common code.
BUG= building pnacl-llc.nexe for MIPS fails
TEST= build sandboxed tools for MIPS
R=mseaborn@chromium.org
Review URL: https://codereview.chromium.org/46193002
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See:
http://llvm.org/viewvc/llvm-project?view=revision&revision=187787
The newer version of newlib tickles this x86-32 bug
when building the exception handling tests, which don't
strip the "tail" attribute.
BUG=https://code.google.com/p/nativeclient/issues/detail?id=3702
Waiting on trybots, but it seems to have fixed the minimal
reproducer I have:
http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-linux-pnacl-x86_64/builds/922
http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-linux-pnacl-x86_32/builds/870
http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-mac-pnacl-x86_32/builds/875
R=jfb@chromium.org
Review URL: https://codereview.chromium.org/26538008
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Cherry-pick r192124 from upstream.
Original commit message:
Author: Akira Hatanaka <ahatanaka@mips.com>
Date: Mon Oct 7 19:13:53 2013 +0000
[mips] Disable tail merging when long branch pass is enabled.
Another bug-fix in LongBranchPass, exposed in llc when it is compiled with
LLVM, and visible in NativeClient through llc.nexe.
TBR= mseaborn@chromium.org, dschuff@chromium.org
BUG= bug in llc.nexe for MIPS
Review URL: https://codereview.chromium.org/26963003
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Cherry-pick r192122 from upstream.
Original commit message:
Author: Akira Hatanaka <ahatanaka@mips.com>
Date: Mon Oct 7 19:06:57 2013 +0000
[mips] Define method MipsSubtarget::enableLongBranchPass.
This is a helper function/change for a subsequent fix in LongBranchPass,
so we need to cherrypick it to be able to pick the next change as is.
TBR= mseaborn@chromium.org, dschuff@chromium.org
Review URL: https://codereview.chromium.org/26754006
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Cherry-pick r191978 from upstream.
Original commit message:
Author: Akira Hatanaka <ahatanaka@mips.com>
Date: Fri Oct 4 20:51:40 2013 +0000
[mips] Fix a bug in MipsLongBranch::replaceBranch, which was erasing
instructions in delay slots along with the original branch instructions
This has to be cherrypicked, as it is a bug in backend. It was exposed in
a long function inside of llc, which caused llc.nexe to work incorrectly.
TBR= mseaborn@chromium.org, dschuff@chromium.org
BUG= bug in MIPS backend
Review URL: https://codereview.chromium.org/26933005
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Cherry-pick r187244 from upstream.
Original commit message:
Author: Akira Hatanaka <ahatanaka@mips.com>
Date: Fri Jul 26 20:58:55 2013 +0000
[mips] Implement llvm.trap intrinsic.
Patch by Sasa Stankovic.
This has to be cherrypicked, as two tests fail due to missing llvm.trap
intrinsic. The tests are:
- run_sysbrk_test
- run_abi_types_test
TBR= mseaborn@chromium.org, dschuff@chromium.org
BUG= sysbrk and abi_types tests fail for MIPS
Review URL: https://codereview.chromium.org/26953003
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Cherry-pick r182306 from upstream.
Original commit message:
Author: Akira Hatanaka <ahatanaka@mips.com>
Date: Mon May 20 18:07:43 2013 +0000
[mips] Trap on integer division by zero.
By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.
TBR= mseaborn@chromium.org, dschuff@chromium.org
BUG= missing trap for MIPS
Review URL: https://codereview.chromium.org/26846007
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LowerNaClTargetArch has to return const PnaclTargetArchitectureMips_32 for
MIPS. The constant is later used in ResolvePNaClIntrinsics pass.
BUG= https://code.google.com/p/nativeclient/issues/detail?id=3602
R=jfb@chromium.org
Review URL: https://codereview.chromium.org/25887007
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Currently when a function uses floating-point callee-saved registers, it does not emit unwind info for adjusting the CFA and showing the locations of the saved registers on the stack. This results in the unwinder getting a bad value for the return address when it attempts to unwind past the function's frame, which breaks gdb backtracing and exception handling unwinding. Add to the existing MachineMoves describing the CFA and register locations to handle the float registers
BUG= https://code.google.com/p/nativeclient/issues/detail?id=3670
R=jvoung@chromium.org
Review URL: https://codereview.chromium.org/23691041
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Localmods came from: https://codereview.chromium.org/10825082/, and earlier.
(1) The original change was so that byval parameters always
go on the stack. That part was added because the original
ARM code was buggy, and did not actually make a copy of the
value, modifying the caller's struct (ouch!).
(2) Then came a localmod to make all arguments following a
byval go on the stack and to make the var-args code aware of
that. This is so that arguments stay in the correct order
for var-args to pick up.
For (1) there has been some work upstream to make it work
better. In any case, clang with --target=armv7a-...-gnueabi
only used byval in some limited cases -- when the size of
the struct is > 64 bytes where the backend will know
that part of it could be in regs, and the rest can be
memcpy'ed to the stack.
For le32, clang will still generate byval without
satisfying the same ARM condition (only for structs
bigger than 64 bytes), so it could be *very bad* if
we didn't have the ABI simpification passes rewrite
the byval and try to let the ARM backend do things
with byval...
TEST=the GCC torture tests: va-arg-4.c, and 20030914-2.c
and the example in issue 2746 still pass.
BUG=none, cleanup
R=dschuff@chromium.org
Review URL: https://codereview.chromium.org/23691009
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It was used to support old r9/TLS model:
https://codereview.chromium.org/11345042/
BUG=none (cleanup)
R=jfb@chromium.org
Review URL: https://codereview.chromium.org/23135011
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Prevent sandbox addresses from being written to the stack. This
covers the following cases:
1. Function calls manually push a masked return address and jump to
the target, rather than using the call instruction.
2. When the function prolog chooses to use a frame pointer (rbp), it
saves a masked version of the old rbp.
3. Indirect branches (jumps, calls, and returns) uniformly use r11 to
construct the 64-bit target address.
4. Register r11 is marked as reserved (similar to r15) so that the
register allocator won't inadvertently spill a code address to the
stack.
These transformations can be disabled for performance testing with the
flag "-sfi-hide-sandbox-base=false".
BUG= https://code.google.com/p/nativeclient/issues/detail?id=1235
R=eliben@chromium.org, mseaborn@chromium.org
Review URL: https://codereview.chromium.org/19505003
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Several parts of the already in-place code have been omitted in the previous
merge. These are:
- missing lowering of Intrinsic::nacl_read_tp;
- checks for forbidden instructiosn in branch-delay slots;
- lowering operation for ISD::NACL_TP_TLS_OFFSET and ISD::NACL_TP_TDB_OFFSET.
BUG= https://code.google.com/p/nativeclient/issues/detail?id=2275
TEST= run smoke tests
R=eliben@chromium.org
Review URL: https://codereview.chromium.org/19614006
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Specifically:
r186489 - Fix ARMFastISel::ARMEmitIntExt shift emission
r183794 - ARM FastISel fix sext/zext fold
r183601 - Fix unused variable warning from my previous patch
r183551 - ARM FastISel integer sext/zext improvements
These should fix some failures that I had run into back then, as well as make ARM FastISel faster because it doesn't go to SelectionDAG.
BUG= https://code.google.com/p/nativeclient/issues/detail?id=3501
R=jvoung@chromium.org
TEST= make check-all
Review URL: https://codereview.chromium.org/19992002
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BUG=None
R=dschuff@chromium.org
Review URL: https://codereview.chromium.org/19472003
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on ARM fail
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