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2012-09-26Add SARX/SHRX/SHLX code generation supportMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164675 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26Add RORX code generation supportMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164674 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26Add MULX code generation supportMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164673 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26Remove hasNoAVX method. Can just invert hasAVX instead.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26Add 'lock' prefix output support in assembly printerMichael Liao
- Instead of embedding 'lock' into each mnemonic of atomic instructions except 'xchg', we teach X86 assembly printer to output 'lock' prefix similar to or consistent with code emitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164659 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25Merge commit 'bc4021f31eaa97ee52655828da3e3de14a39e4a6'Derek Schuff
Conflicts: lib/MC/MCAssembler.cpp lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/Mips/MipsInstrFPU.td lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp lib/Target/X86/X86ISelLowering.h
2012-09-25Initialize boolean variables in MipsSubtarget's constructor.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164642 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25blank line for test commitReed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164640 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25TargetLowering interface to set/get minimum block entries for jump tables.Sebastian Pop
Provide interface in TargetLowering to set or get the minimum number of basic blocks whereby jump tables are generated for switch statements rather than an if sequence. getMinimumJumpTableEntries() defaults to 4. setMinimumJumpTableEntries() allows target configuration. This patch changes the default for the Hexagon architecture to 5 as it improves performance on some benchmarks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164628 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25Add missing i64 max/min/umax/umin on 32-bit targetMichael Liao
- Turn on atomic6432.ll and add specific test case as well git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164616 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25ARM: Darwin BL/BLX relocations to out-of-range symbols.Jim Grosbach
When a BL/BLX references a symbol in the same translation unit that is out of range, use an external relocation. The linker will use this to generate a branch island rather than a direct reference, allowing the relocation to resolve correctly. rdar://12359919 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164615 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25Consistently specify the assembly variant to MatchInstructionImpl.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164611 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25Fix an illegal tailcall opt where the callee returns a double via xmm while ↵Evan Cheng
caller returns x86_fp80 via st0. rdar://12229511 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164588 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25ARM: 'add Rd, pc, #imm' is an alias for 'adr Rd, #imm'.Jim Grosbach
rdar://9795790 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164577 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Mark jump tables in code sections with DataRegion directives.Jim Grosbach
Even out-of-line jump tables can be in the code section, so mark them as data-regions for those targets which support the directives. rdar://12362871&12362974 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164571 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Rather then have a wrapper function, have tblgen instantiate the implementation.Chad Rosier
Also remove an unused argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164567 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Specify MachinePointerInfo as refering to the argument value and offset of theRoman Divacky
store when handling byval arguments. Thus preventing reordering of the store with load with post-RA scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164553 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Rather then have a wrapper function, have tblgen instantiate the implementation.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164548 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-22ARMInstPrinter.cpp: Fix a warning in -Asserts. [-Wunused-variable]NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164459 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-22Whitespace.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164458 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-22Fix edge cases of ARM shift operands in arith instructions.Tim Northover
As before with load instructions, oddities like "asr #32", "rrx" could be printed incorrectly. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164456 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-22Fix the handling of edge cases in ARM shifted operands.Tim Northover
This patch fixes load/store instructions to handle less common cases like "asr #32", "rrx" properly throughout the MC layer. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164455 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-22Fix 16-bit atomic inst encoding and keep pseudo-inst starting with '#'Michael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164453 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-22Fix typo in r164357Michael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164452 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-22MIPS DSP: Add immediate leaves.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164435 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-22MIPS DSP: Add predicates and instruction template.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164434 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Add MIPS DSP register classes. Set actions of DSP vector operations and overrideAkira Hatanaka
TargetLowering's callback functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164431 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21SelectionDAG node enums for MIPS DSP nodes.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164430 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Add MIPS accumulator and DSP control registers.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164429 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Add flags and feature bits for mips dsp.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164428 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21[ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164420 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Add comment.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164415 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Add comment.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164414 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21[fast-isel] Fallback to SelectionDAG isel if we require strict alignment forChad Rosier
non-aligned i32 loads/stores. rdar://12304911 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164381 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Fix a typo in r164357Michael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164372 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Make the 'get*AlignmentFromAttr' functions into member functions within the ↵Bill Wendling
Attributes class. Now with fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164370 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Cortex-A9 latency fixes (w/ -schedmodel only).Andrew Trick
Quick review against the manual revealed a few obvious mistakes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164361 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Add missing i8 max/min/umax/umin supportMichael Liao
- Fix PR5145 and turn on test 8-bit atomic ops git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164358 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Revise td of X86 atomic instructionsMichael Liao
- Rewirte most atomic instructions in templates for both better maintenance and future extensions, such as HLE in TSX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164357 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Mips16FrameLowering.cpp: Remove unused TII introduced in r164349. ↵NAKAMURA Takumi
[-Wunused-variable] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164354 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Properly save and restore RA and Mips16 callee save registers S0,S1Akira Hatanaka
Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164349 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21[fast-isel] Fallback to SelectionDAG isel if we require strict alignment forChad Rosier
non-halfword-aligned i16 loads/stores. rdar://12304911 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164345 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Tidy up. Whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164344 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Tidy up. Formatting.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164343 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21ARM: Use a dedicated intrinsic for vector bitwise select.Jim Grosbach
The expression based expansion too often results in IR level optimizations splitting the intermediate values into separate basic blocks, preventing the formation of the VBSL instruction as the code author intended. In particular, LICM would often hoist part of the computation out of a loop. rdar://11011471 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164340 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-20Revert r164308 to fix buildbots.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164309 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-20Make the 'get*AlignmentFromAttr' functions into member functions within the ↵Bill Wendling
Attributes class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164308 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-20Change enum type in a static table to uint8_t instead. Saves about 700 ↵Craig Topper
hundred bytes of static data. Change unsigned char in same table to uint8_t for explicitness. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164285 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-20Re-work X86 code generation of atomic ops with spin-loopMichael Liao
- Rewrite/merge pseudo-atomic instruction emitters to address the following issue: * Reduce one unnecessary load in spin-loop previously the spin-loop looks like thisMBB: newMBB: ld t1 = [bitinstr.addr] op t2 = t1, [bitinstr.val] not t3 = t2 (if Invert) mov EAX = t1 lcs dest = [bitinstr.addr], t3 [EAX is implicit] bz newMBB fallthrough -->nextMBB the 'ld' at the beginning of newMBB should be lift out of the loop as lcs (or CMPXCHG on x86) will load the current memory value into EAX. This loop is refined as: thisMBB: EAX = LOAD [MI.addr] mainMBB: t1 = OP [MI.val], EAX LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined] JNE mainMBB sinkMBB: * Remove immopc as, so far, all pseudo-atomic instructions has all-register form only, there is no immedidate operand. * Remove unnecessary attributes/modifiers in pseudo-atomic instruction td * Fix issues in PR13458 - Add comprehensive tests on atomic ops on various data types. NOTE: Some of them are turned off due to missing functionality. - Revise tests due to the new spin-loop generated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164281 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19Merge commit '020aba0c3b6092e353e133446cb6453f95f0d61b'Derek Schuff
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2026-11-13 19:44:59 +0000