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2012-10-03Remove a localmod that may have disabled an ARMLoadStoreJan Voung
optimization more often than necessary. The upstream fix was merged in a while back. BUG= http://code.google.com/p/nativeclient/issues/detail?id=2575 TEST= pnacl/test.sh test-arm-sbtc toolchain_tests && spec translator test on arm for gcc and eon. Review URL: https://codereview.chromium.org/11051017
2012-10-03Add methods which query for the specific attribute instead of using theBill Wendling
enums. This allows for better encapsulation of the Attributes class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165132 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03Set up MCSchedModel after detecting the CPU type in X86SubTarget.Preston Gurd
Corrects a problem whereby MCSchedModel was not being set up when the CPU type was auto-detected. Patch by Andy Zhang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03Revert 165051-165049 while looking into the foreach.m failure inEric Christopher
more detail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165099 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03Fix 80-column violationCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165089 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03The early if conversion pass is ready to be used as an opt-in.Jakob Stoklund Olesen
Enable the pass by default for targets that request it, and change the -enable-early-ifcvt to the opposite -disable-early-ifcvt. There are still some x86 regressions when enabling early if-conversion because of the missing machine models. Disable the pass for x86 until machine models are added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Fix a serious X86 instruction selection bug. InEvan Cheng
X86DAGToDAGISel::PreprocessISelDAG(), isel is moving load inside callseq_start / callseq_end so it can be folded into a call. This can create a cycle in the DAG when the call is glued to a copytoreg. We have been lucky this hasn't caused too many issues because the pre-ra scheduler has special handling of call sequences. However, it has caused a crash in a specific tailcall case. rdar://12393897 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165072 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Revert "Don't use a debug location for frame setup instructions in the"Eric Christopher
This reverts 165055 and 165052 temporarily while I look at debugger failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165071 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Revert 165057, per Jim's request. This requires further discussion.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165069 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02The mips 64bit instructions DSLL, DSRA, DSRL, DEXT and DINS get transformed ↵Jack Carter
by the assembler or through codegen direct object output to other variants based on the value of the immediate values of the operands. If the code is generated as assembler, this transformation does not occur assuming that it will occur later in the assembler. This code was originally called from MipsAsmPrinter.cpp and we needed to check for OutStreamer.hasRawTextSupport(). This was not a good place for it and has been moved to MCTargetDesc/MipsMCCodeEmitter.cpp where both direct object and the assembler use it it automagically. The test cases have been checked in for a number of weeks now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165067 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Make sure to put our sret argument into %rax on x86-64. Fixes PR13563!Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165063 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02[ms-inline asm] Add basic support for wildcard MCParsedAsmOperands. This typeChad Rosier
of operand is specific to MS-style inline assembly and should not be generated when parsing normal assembly. The purpose of the wildcard operands are to allow the AsmParser to match multiple instructions (i.e., MCInsts) to a given ms-style asm statement. For the time being the matcher just returns the first match. This patch only implements wildcard matches for memory operands. Support for register wildcards will be added in the near future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165057 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Don't use a debug location for frame setup instructions in theEric Christopher
prologue. Also skip frame setup instructions when looking for the first location. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165052 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Use the existing DebugLoc.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165051 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Make the location a parameter since we may not want the next oneEric Christopher
in the block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165050 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Remove the SavePoint infrastructure from fast isel, replaceEric Christopher
with just an insert point from the MachineBasicBlock and let the location be updated as we access it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165049 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Support for generating ELF objects on Windows.Andrew Kaylor
This adds 'elf' as a recognized target triple environment value and overrides the default generated object format on Windows platforms if that value is present. This patch also enables MCJIT tests on Windows using the new environment value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165030 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-01[ms-inline asm] Add the convertToMapAndConstraints() function that is used toChad Rosier
map constraints and MCInst operands to inline asm operands. This replaces the getMCInstOperandNum() function. The logic to determine the constraints are not in place, so we still default to a register constraint (i.e., "r"). Also, we no longer build the MCInst but rather return just the opcode to get the MCInstrDesc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164979 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-01MachO: direct-to-object attribute for data-in-code markers.Jim Grosbach
The target backend can support data-in-code load commands even when the assembler doesn't, or vice-versa. Allow targets to opt-in for direct-to-object. PR13973. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164974 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-01Merge commit '72f0976c1b91c7ba50dce4d0ad0289dc14d37f81'Derek Schuff
Conflicts: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsSubtarget.cpp
2012-10-01Use constants for all return values in switch. Allows clang to optimize it ↵Craig Topper
into a lookup table. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164926 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-30Change getX86SubSuperRegister to take an MVT::SimpleValueType rather than an ↵Craig Topper
EVT and add llvm_unreachable to the switches. Helps it compile to dramatically better code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164919 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-29Add LLVM support for Swift.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164899 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-29Whitespace.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-29Shrink TargetAlignElem a bit, we do a lot of searches on them.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164897 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-28MIPS DSP: other miscellaneous instructions.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164845 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-28MIPS DSP: ADDUH.QB instruction sub-class.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164840 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-28X86: when replacing SUB with TEST in ISelDAGToDAG, only replace uses of theManman Ren
second output of SUB with first output of TEST. PR13966 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164835 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-281. Add load/store words from the stackReed Kotler
2. As part of this, added assembly format FEXT_RI16_SP_explicit_ins and moved other lines for FEXT_RI16 formats to be in the right place in the code. 3. Added mayLoad and mayStore assignements for the load/store instructions added and for ones already there that did not have this assignment. 4. Another patch will deal with the problem of load/store byte/halfword to the stack. This is a particular Mips16 problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164811 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: ABSQ_S.PH instruction sub-class.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164787 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: SHLL.QB instruction sub-class.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164786 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. ↵Sylvestre Ledru
See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27Fix a typo 'iff' => 'if'Sylvestre Ledru
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164767 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27[arm-fast-isel] Add support for ELF PIC.Jush Lu
This is a preliminary step towards ELF support; currently ARMFastISel hasn't been used for ELF object files yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164759 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: rddsp (instruction which reads DSPControl register fields to a GPR).Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164756 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: CMPU.EQ.QB instruction sub-class.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164755 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: ADDU.QB instruction sub-class.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164754 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos ↵Akira Hatanaka
Field instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164751 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: all the remaining instructions which read or write accumulators.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164750 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: add support for extract-word instructions.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164749 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: add functions which decode DSP and accumulator registers.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164748 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: add code necessary for pseudo instruction lowering.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164747 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: add bitcast patterns between vectors and int.Akira Hatanaka
No test cases. These patterns will get tested along with dsp intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164746 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: add vector load/store patterns.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164744 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26Remove the `hasFnAttr' method from Function.Bill Wendling
The hasFnAttr method has been replaced by querying the Attributes explicitly. No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164725 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26X86_32: Large Symbol+Offset relocations.Jim Grosbach
If the offset is more than 24-bits, it won't fit in a scattered relocation offset field, so we fall back to using a non-scattered relocation. rdar://12358909 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164724 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26Add case clauses for returning dsp accumulator encoding values in functionAkira Hatanaka
getMipsRegisterNumbering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164720 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26Add DSP accumulator registers and register class. Remove hi/lo registers.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164719 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26Delete member MipsFunctionInfo::OutArgFIRange and code that accesses it.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164718 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.James Molloy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164685 91177308-0d34-0410-b5e6-96231b3b80d8
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