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2013-03-15ARM cost model: Fix cost of fptrunc and fpext instructionsArnold Schwaighofer
A vector fptrunc and fpext simply gets split into scalar instructions. radar://13192358 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177159 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15Protect PPC Altivec patterns with a predicateHal Finkel
In preparation for the addition of other SIMD ISA extensions (such as QPX) we need to make sure that all Altivec patterns are properly predicated on having Altivec support. No functionality change intended (one test case needed to be updated b/c it assumed that Altivec intrinsics would be supported without enabling Altivec support). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177152 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15Allocate the RS spill slot for any PPC function with spills and a large ↵Hal Finkel
stack frame For spills into a large stack frame, the FI-elimination code uses the register scavenger to obtain a free GPR for use with an r+r-addressed load or store. When there are no available GPRs, the scavenger gets one by using its spill slot. Previously, we were not always allocating that spill slot and the RS would assert when the spill slot was needed. I don't currently have a small test that triggered the assert, but I've created a small regression test that verifies that the spill slot is now added when the stack frame is sufficiently large. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177140 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15Silence anonymous type in anonymous union warnings.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Unaligned loads should use the VMOVUPS opcode.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177130 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Remove some unused variables to clean the Clang -Werror buildDavid Blaikie
(these were added in r177089) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177129 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14[mips] Set isAllocatable bit of unallocatable register classes to 0.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177128 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Prepare for adding InstrSchedModel annotations to X86 instructions.Jakob Stoklund Olesen
The new InstrSchedModel is easier to use than the instruction itineraries. It will be used to model instruction latency and throughput in modern Intel microarchitectures like Sandy Bridge. InstrSchedModel should be able to coexist with instruction itinerary classes, but for cleanliness we should switch the Atom processor model to the new InstrSchedModel as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177122 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Add a new method which enables one to change register classes.Reed Kotler
See the Mips16ISetLowering.cpp patch to see a use of this. For now now the extra code in Mips16ISetLowering.cpp is a nop but is used for test purposes. Mips32 registers are setup and then removed and then the Mips16 registers are setup. Normally you need to add register classes and then call computeRegisterProperties. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177120 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14[fast-isel] The X86FastISel::FastLowerArguments function doesn't properly handleChad Rosier
the win64 calling convention. rdar://13423768 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177113 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Move estimateStackSize from ARM into MachineFrameInfoHal Finkel
This is a generic function (derived from PEI); moving it into MachineFrameInfo eliminates a current redundancy between the ARM and AArch64 backends, and will allow it to be used by the PowerPC target code. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177111 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Provide the register scavenger to processFunctionBeforeFrameFinalizedHal Finkel
Add the current PEI register scavenger as a parameter to the processFunctionBeforeFrameFinalized callback. This change is necessary in order to allow the PowerPC target code to set the register scavenger frame index after the save-area offset adjustments performed by processFunctionBeforeFrameFinalized. Only after these adjustments have been made is it possible to estimate the size of the stack frame. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177108 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Use frame-index scavenging for PPC register spillingHal Finkel
Make requiresFrameIndexScavenging return true, and create virtual registers in the spilling code instead of using the register scavenger directly. This makes the target-level code simpler, and importantly, delays the scavenging until after callee-saved register processing (which will be important for later changes). Also cleans up trackLivenessAfterRegAlloc (makes it inline in the header with the other related functions). This makes it clear that it always returns true. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177107 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Not all PPC functions with a frame pointer need a RS spill slotHal Finkel
We used to add a spill slot for the register scavenger whenever the function has a frame pointer. This is unnecessarily conservative: We may need the spill slot for dynamic stack allocations, and functions with dynamic stack allocations always have a FP, but we might also have a FP for other reasons (such as the user explicitly disabling frame-pointer elimination), and we don't necessarily need a spill slot for those functions. The structsinregs test needed adjustment because it disables FP elimination. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177106 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14ARM cost model: Increase cost of some vector selects we do terrible onArnold Schwaighofer
By terrible I mean we store/load from the stack. This matters on PAQp8 in _Z5trainPsS_ii (which is inlined into Mixer::update) where we decide to vectorize a loop with a VF of 8 resulting in a 25% degradation on a cortex-a8. LV: Found an estimated cost of 2 for VF 8 For instruction: icmp slt i32 LV: Found an estimated cost of 2 for VF 8 For instruction: select i1, i32, i32 The bug that tracks the CodeGen part is PR14868. radar://13403975 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177105 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14[mips] Fix filename in comment and delete unnecessary lines of code.Akira Hatanaka
No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177104 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Hexagon: Removed asserts regarding alignment and offset.Jyotsna Verma
We are warning the user about the alignment, so we should not assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177103 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Add back lines which were accidentally deleted in CMakeLists.txt.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177096 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14[mips] Define function MipsSEDAGToDAGISel::selectAddESubE.Akira Hatanaka
No intended functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177095 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Add a comment about overlapping PPC frame offsetsHal Finkel
I don't think that it is otherwise clear how the overlapping offsets are processed into distinct spill slots. Comment that this is done in processFunctionBeforeFrameFinalized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177094 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14[mips] Rename functions and variables to start with proper case.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177092 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Add header file MipsISelDAGToDAG.h.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177090 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14[mips] Define two subclasses of MipsDAGToDAGISel. Mips16DAGToDAGISel is forAkira Hatanaka
mips16 and MipsSEDAGToDAGISel is for mips32/64. No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177089 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14R600: Factorize code handling Const Read Port limitationVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177078 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Fix the name of a variable to match its declaration. Fixes build failure ↵Craig Topper
from r177014. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177015 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Fix a bug in the calculation of the VEX.B bit for FMA4 rr with the VEX.W bit ↵Craig Topper
set. The VEX.B was being calculated from the wrong operand. Fixes at least some portion of PR14185. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177014 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Teach X86 MC instruction lowering that VMOVAPSrr and other VEX-encoded ↵Craig Topper
register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not. This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177011 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Fix PR15309Michael Liao
- Fix the typo on type checking git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177010 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13Reset some of the target options which affect code generation.Bill Wendling
This doesn't reset all of the target options within the TargetOptions object. This is because some of those are ABI-specific and must be determined if it's okay to change those on the fly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13R600: Remove unused Outputs variableVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176967 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13Add one more overload to make VS2008's debug mody happy.Benjamin Kramer
sigh. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176946 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is forAkira Hatanaka
mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176917 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-12ARM cost model: Increase the cost for vector casts that use the stackArnold Schwaighofer
Increase the cost of v8/v16-i8 to v8/v16-i32 casts and truncates as the backend currently lowers those using stack accesses. This was responsible for a significant degradation on MultiSource/Benchmarks/Trimaran/enc-pc1/enc-pc1 where we vectorize one loop to a vector factor of 16. After this patch we select a vector factor of 4 which will generate reasonable code. unsigned char cle[32]; void test(short c) { unsigned short compte; for (compte = 0; compte <= 31; compte++) { cle[compte] = cle[compte] ^ c; } } radar://13220512 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176898 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-12Don't reserve R2 on Darwin/PPCHal Finkel
Now that only the register-scavenger version of the CR spilling code remains, we no longer need the Darwin R2 hack. Darwin can use R0 as a spare register in any case where the System V ABI uses it (R0 is special architecturally, and so is reserved under all common ABIs). A few test cases needed to be updated to reflect the register-allocation changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176868 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-12PPC should always use the register scavenger for CR spillingHal Finkel
This removes the -disable-ppc[32|64]-regscavenger options; the code that uses the register scavenger has been working well (and has been the default) for some time, and we don't need options to enable the old (broken) CR spilling code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176865 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-12[mips] Rename function and variable names to start with proper case. Fix typos.Akira Hatanaka
Delete commented-out code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176844 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11Merge commit '279b9184c2ff4fea93b198a3519b8cb3a1d8d195'Eli Bendersky
Conflicts: include/llvm/CodeGen/LexicalScopes.h include/llvm/MC/MCAsmInfo.h lib/Linker/LinkArchives.cpp lib/Linker/LinkItems.cpp lib/MC/MCAsmInfo.cpp lib/MC/MCDwarf.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp lib/Target/Mips/MipsAsmPrinter.cpp lib/Target/Mips/MipsDelaySlotFiller.cpp lib/Target/Mips/MipsISelDAGToDAG.cpp lib/Target/Mips/MipsSubtarget.cpp lib/Target/Mips/MipsSubtarget.h lib/Target/Mips/MipsTargetObjectFile.cpp lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86TargetMachine.cpp lib/Transforms/CMakeLists.txt lib/Transforms/LLVMBuild.txt lib/Transforms/Makefile test/MC/ARM/arm_instructions.s test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s
2013-03-11Fixes disassembler crashes on 2013 Haswell RTM instructions.Kevin Enderby
rdar://13318048 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176828 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11R600: Fix JUMP handling so that MachineInstr verification can occurVincent Lejeune
This allows R600 Target to use the newly created -verify-misched llc flag git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176819 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11R600MachineScheduler.cpp: Fix use cases of dbgs(). Don't include <iostream> ↵NAKAMURA Takumi
here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176797 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-10Correct this error message, and most importantly make it distinct from theNick Lewycky
error above. Based on a patch by Peter Zotov! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176794 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-10Cleanup #includes.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176787 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-09Don't glue users to extract_subreg when selecting the llvm.arm.ldrexdLang Hames
intrinsic - it can cause impossible-to-schedule subgraphs to be introduced. PR15053. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176777 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-09TLI: Microoptimize calls to strlen+memcmp to strncmp.Benjamin Kramer
The strlen+memcmp was hidden in a call to StringRef::operator==. We check if there are any null bytes in the string upfront so we can simplify the comparison Small speedup when compiling code with many function calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176766 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08R600: Optimize another selectcc caseTom Stellard
fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne -> selectcc x, y, a, b, cc Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176700 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08R600: Improve custom lowering of select_ccTom Stellard
Two changes: 1. Prefer SET* instructions when possible 2. Handle the CND*_INT case with floating-point args Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176699 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08R600: Change operation action from Custom to Expand for BR_CCTom Stellard
Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176698 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08R600: Change operation action from Custom to Expand for SETCCTom Stellard
Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176697 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08R600: Set BooleanContents to ZeroOrNegativeOneBooleanContentTom Stellard
Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176696 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08DAGCombiner: Use correct value type for checking legality of BR_CC v3Tom Stellard
LegalizeDAG.cpp uses the value of the comparison operands when checking the legality of BR_CC, so DAGCombiner should do the same. v2: - Expand more BR_CC value types for NVPTX v3: - Expand correct BR_CC value types for Hexagon, Mips, and XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176694 91177308-0d34-0410-b5e6-96231b3b80d8
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