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2013-11-22support 8-bit constantsAlon Zakai
2013-11-22ir debugger helperAlon Zakai
2013-11-22make assert show something even in release buildsAlon Zakai
2013-11-22fix relooper branch directionsAlon Zakai
2013-11-22set asm mode in relooper and add label varAlon Zakai
2013-11-22Math.imulAlon Zakai
2013-11-22native phi pushingAlon Zakai
2013-11-22preparation for phi pushingAlon Zakai
2013-11-22update relooper and fix indentation and empty linesAlon Zakai
2013-11-22more mathopsAlon Zakai
2013-11-22fix getOpName - we have no problem with forward refsAlon Zakai
2013-11-22more debug infoAlon Zakai
2013-11-22note each instruction in a debug messageAlon Zakai
2013-11-22fail on invalid getOpName valuesAlon Zakai
2013-11-22improve pre-relooper branch parsingAlon Zakai
2013-11-22remove phi printing code, in preparation for pushing them back into branchesAlon Zakai
2013-11-21fix mathop return typeAlon Zakai
2013-11-21fix sitofp return typeAlon Zakai
2013-11-21fix sitofp castAlon Zakai
2013-11-21merge in CppBackend workAlon Zakai
2013-10-30Move global FlagSfi variables to common modulePetar Jovanovic
When built as nexe, llc is configured and built for one arch only. Variables FlagSfiData, FlagSfiLoad, FlagSfiStore, FlagSfiStack, and FlagSfiBranch have to availabe for MIPS as well, so this change moves them from ARM-only code to common code. BUG= building pnacl-llc.nexe for MIPS fails TEST= build sandboxed tools for MIPS R=mseaborn@chromium.org Review URL: https://codereview.chromium.org/46193002
2013-10-11Cherry-pick LLVM 187787 to prevent tail calls on x86-32 when not appropriate.Jan Voung
See: http://llvm.org/viewvc/llvm-project?view=revision&revision=187787 The newer version of newlib tickles this x86-32 bug when building the exception handling tests, which don't strip the "tail" attribute. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3702 Waiting on trybots, but it seems to have fixed the minimal reproducer I have: http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-linux-pnacl-x86_64/builds/922 http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-linux-pnacl-x86_32/builds/870 http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-mac-pnacl-x86_32/builds/875 R=jfb@chromium.org Review URL: https://codereview.chromium.org/26538008
2013-10-11Apply upstream: [mips] Disable tail merging when long branch pass is enabled.Petar Jovanovic
Cherry-pick r192124 from upstream. Original commit message: Author: Akira Hatanaka <ahatanaka@mips.com> Date: Mon Oct 7 19:13:53 2013 +0000 [mips] Disable tail merging when long branch pass is enabled. Another bug-fix in LongBranchPass, exposed in llc when it is compiled with LLVM, and visible in NativeClient through llc.nexe. TBR= mseaborn@chromium.org, dschuff@chromium.org BUG= bug in llc.nexe for MIPS Review URL: https://codereview.chromium.org/26963003
2013-10-11Apply upstream: [mips] Define method MipsSubtarget::enableLongBranchPass.Petar Jovanovic
Cherry-pick r192122 from upstream. Original commit message: Author: Akira Hatanaka <ahatanaka@mips.com> Date: Mon Oct 7 19:06:57 2013 +0000 [mips] Define method MipsSubtarget::enableLongBranchPass. This is a helper function/change for a subsequent fix in LongBranchPass, so we need to cherrypick it to be able to pick the next change as is. TBR= mseaborn@chromium.org, dschuff@chromium.org Review URL: https://codereview.chromium.org/26754006
2013-10-11Apply upstream: [mips] Fix a bug in MipsLongBranch::replaceBranchPetar Jovanovic
Cherry-pick r191978 from upstream. Original commit message: Author: Akira Hatanaka <ahatanaka@mips.com> Date: Fri Oct 4 20:51:40 2013 +0000 [mips] Fix a bug in MipsLongBranch::replaceBranch, which was erasing instructions in delay slots along with the original branch instructions This has to be cherrypicked, as it is a bug in backend. It was exposed in a long function inside of llc, which caused llc.nexe to work incorrectly. TBR= mseaborn@chromium.org, dschuff@chromium.org BUG= bug in MIPS backend Review URL: https://codereview.chromium.org/26933005
2013-10-11Apply upstream: [mips] Implement llvm.trap intrinsic.Petar Jovanovic
Cherry-pick r187244 from upstream. Original commit message: Author: Akira Hatanaka <ahatanaka@mips.com> Date: Fri Jul 26 20:58:55 2013 +0000 [mips] Implement llvm.trap intrinsic. Patch by Sasa Stankovic. This has to be cherrypicked, as two tests fail due to missing llvm.trap intrinsic. The tests are: - run_sysbrk_test - run_abi_types_test TBR= mseaborn@chromium.org, dschuff@chromium.org BUG= sysbrk and abi_types tests fail for MIPS Review URL: https://codereview.chromium.org/26953003
2013-10-11Apply upstream: [mips] Trap on integer division by zero.Petar Jovanovic
Cherry-pick r182306 from upstream. Original commit message: Author: Akira Hatanaka <ahatanaka@mips.com> Date: Mon May 20 18:07:43 2013 +0000 [mips] Trap on integer division by zero. By default, a teq instruction is inserted after integer divide. No divide-by-zero checks are performed if option "-mnocheck-zero-division" is used. TBR= mseaborn@chromium.org, dschuff@chromium.org BUG= missing trap for MIPS Review URL: https://codereview.chromium.org/26846007
2013-10-05[MIPS] Define PnaclTargetArchitectureMips_32Petar Jovanovic
LowerNaClTargetArch has to return const PnaclTargetArchitectureMips_32 for MIPS. The constant is later used in ResolvePNaClIntrinsics pass. BUG= https://code.google.com/p/nativeclient/issues/detail?id=3602 R=jfb@chromium.org Review URL: https://codereview.chromium.org/25887007
2013-09-06Emit MachineMoves for ARM floating point callee-saved registersDerek Schuff
Currently when a function uses floating-point callee-saved registers, it does not emit unwind info for adjusting the CFA and showing the locations of the saved registers on the stack. This results in the unwinder getting a bad value for the return address when it attempts to unwind past the function's frame, which breaks gdb backtracing and exception handling unwinding. Add to the existing MachineMoves describing the CFA and register locations to handle the float registers BUG= https://code.google.com/p/nativeclient/issues/detail?id=3670 R=jvoung@chromium.org Review URL: https://codereview.chromium.org/23691041
2013-08-30Revert some ARM byval localmods since byval+varargs are not in stable pexes.Jan Voung
Localmods came from: https://codereview.chromium.org/10825082/, and earlier. (1) The original change was so that byval parameters always go on the stack. That part was added because the original ARM code was buggy, and did not actually make a copy of the value, modifying the caller's struct (ouch!). (2) Then came a localmod to make all arguments following a byval go on the stack and to make the var-args code aware of that. This is so that arguments stay in the correct order for var-args to pick up. For (1) there has been some work upstream to make it work better. In any case, clang with --target=armv7a-...-gnueabi only used byval in some limited cases -- when the size of the struct is > 64 bytes where the backend will know that part of it could be in regs, and the rest can be memcpy'ed to the stack. For le32, clang will still generate byval without satisfying the same ARM condition (only for structs bigger than 64 bytes), so it could be *very bad* if we didn't have the ABI simpification passes rewrite the byval and try to let the ARM backend do things with byval... TEST=the GCC torture tests: va-arg-4.c, and 20030914-2.c and the example in issue 2746 still pass. BUG=none, cleanup R=dschuff@chromium.org Review URL: https://codereview.chromium.org/23691009
2013-08-19Remove FlagNaClUseM23ArmAbi since M23 was a long time ago.Jan Voung
It was used to support old r9/TLS model: https://codereview.chromium.org/11345042/ BUG=none (cleanup) R=jfb@chromium.org Review URL: https://codereview.chromium.org/23135011
2013-07-24Hide the x86-64 sandbox base address.Jim Stichnoth
Prevent sandbox addresses from being written to the stack. This covers the following cases: 1. Function calls manually push a masked return address and jump to the target, rather than using the call instruction. 2. When the function prolog chooses to use a frame pointer (rbp), it saves a masked version of the old rbp. 3. Indirect branches (jumps, calls, and returns) uniformly use r11 to construct the 64-bit target address. 4. Register r11 is marked as reserved (similar to r15) so that the register allocator won't inadvertently spill a code address to the stack. These transformations can be disabled for performance testing with the flag "-sfi-hide-sandbox-base=false". BUG= https://code.google.com/p/nativeclient/issues/detail?id=1235 R=eliben@chromium.org, mseaborn@chromium.org Review URL: https://codereview.chromium.org/19505003
2013-07-24[MIPS] Fix LLVM merge issuesPetar Jovanovic
Several parts of the already in-place code have been omitted in the previous merge. These are: - missing lowering of Intrinsic::nacl_read_tp; - checks for forbidden instructiosn in branch-delay slots; - lowering operation for ISD::NACL_TP_TLS_OFFSET and ISD::NACL_TP_TDB_OFFSET. BUG= https://code.google.com/p/nativeclient/issues/detail?id=2275 TEST= run smoke tests R=eliben@chromium.org Review URL: https://codereview.chromium.org/19614006
2013-07-22Cherrypick upstream ARM FastISel ext patchesJF Bastien
Specifically: r186489 - Fix ARMFastISel::ARMEmitIntExt shift emission r183794 - ARM FastISel fix sext/zext fold r183601 - Fix unused variable warning from my previous patch r183551 - ARM FastISel integer sext/zext improvements These should fix some failures that I had run into back then, as well as make ARM FastISel faster because it doesn't go to SelectionDAG. BUG= https://code.google.com/p/nativeclient/issues/detail?id=3501 R=jvoung@chromium.org TEST= make check-all Review URL: https://codereview.chromium.org/19992002
2013-07-19Clean up a debug printout left in by mistake during the 3.3 mergeEli Bendersky
BUG=None R=dschuff@chromium.org Review URL: https://codereview.chromium.org/19472003
2013-07-18Merge remote-tracking branch 'origin/master'Eli Bendersky
2013-07-18Correctly adjust LOCALMOD for x64 frame register computation.Eli Bendersky
2013-07-17Fixed constpool pattern matching problem that made the crtbeginS buildEli Bendersky
on ARM fail
2013-07-17Remove unnecessary debug printoutEli Bendersky
2013-07-17Disallow a global address in the x86-64 displacement field.Jim Stichnoth
This applies only to %r15 sandboxed memory references. The problem is that if the index register is negative, the sandboxing operation will cause the index to become a large positive 32-bit value, which combined with the displacement, will overflow and try to reference memory outside the sandbox. This situation may legitimately occur if the compiler happens to construct a (constant) interior pointer to the middle of the global struct/array, and then dereferences it with a variable offset. After this fix, pnacl/scripts/testsuite_known_failures_pnacl.txt can be updated to remove the "aha x86-64" known failure. BUG= https://code.google.com/p/nativeclient/issues/detail?id=3517 R=eliben@chromium.org Review URL: https://codereview.chromium.org/17987002
2013-07-16More tests passEli Bendersky
2013-07-16Fixing make check errors...Eli Bendersky
2013-07-16Make it compileEli Bendersky
2013-07-15Trying to get the thing to copmile...Eli Bendersky
2013-07-15Merge commit '7dfcb84fc16b3bf6b2379713b53090757f0a45f9'Eli Bendersky
Conflicts: docs/LangRef.rst include/llvm/CodeGen/CallingConvLower.h include/llvm/IRReader/IRReader.h include/llvm/Target/TargetMachine.h lib/CodeGen/CallingConvLower.cpp lib/IRReader/IRReader.cpp lib/IRReader/LLVMBuild.txt lib/IRReader/Makefile lib/LLVMBuild.txt lib/Makefile lib/Support/MemoryBuffer.cpp lib/Support/Unix/PathV2.inc lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMTargetMachine.cpp lib/Target/Mips/CMakeLists.txt lib/Target/Mips/MipsDelaySlotFiller.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsSubtarget.cpp lib/Target/Mips/MipsSubtarget.h lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrControl.td lib/Target/X86/X86InstrFormats.td lib/Transforms/IPO/ExtractGV.cpp lib/Transforms/InstCombine/InstCombineCompares.cpp lib/Transforms/Utils/SimplifyLibCalls.cpp test/CodeGen/X86/fast-isel-divrem.ll test/MC/ARM/data-in-code.ll tools/Makefile tools/llvm-extract/llvm-extract.cpp tools/llvm-link/CMakeLists.txt tools/opt/CMakeLists.txt tools/opt/LLVMBuild.txt tools/opt/Makefile tools/opt/opt.cpp
2013-07-11Fix ARM paired GPR COPY loweringJF Bastien
ARM paired GPR COPY was being lowered to two MOVr without CC. This patch puts the CC back. I sent this patch upstream (with a test) but haven't received a review yet. This seems like a simple oversight in the code, and is holding my atomics patch so I'd like to get it into our repo. R=dschuff@chromium.org TEST= ./scons run_llvm_bitmanip_intrinsics_test platform=arm BUG= no CC on MOVr Review URL: https://codereview.chromium.org/18047006
2013-07-11Sandbox ARM load/store exclusive dualJF Bastien
PNaCl's LLVM sandboxing wasn't correct for ARM load/store exclusive dual. I encountered this while running our testsuite with my atomic changes: the tests which use volatile 64-bit values started failing validation. R=dschuff@chromium.org BUG= validation failure TEST= ./pnacl/test.sh test-arm Review URL: https://codereview.chromium.org/18978015
2013-07-10Fix ARM LDMIA MI.JF Bastien
The instruction that was generated for paired register stack slot load was wrong. This was fixed by Tim Northover in LLVM 3.3 commit 179977, but his patch does much more and doesn't apply as-is to our tree. I'll therefore punt applying the full patch to when we rebase to 3.3. I encountered the issue while working on atomics (64-bit atomics require paired registers on ARM), and saw the 3.3 fix when I tried upstreaming my fix. BUG= non TEST= ./pnacl/test.sh test-arm R=eliben@chromium.org Review URL: https://codereview.chromium.org/18699004
2013-07-09PNaCl: Fix negative relocation addends on x86-32Mark Seaborn
Disable an assertion. This assertion made the behaviour on x86-32 inconsistent with x86-64 and ARM. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3548 TEST=*.ll tests + PNaCl toolchain trybots Review URL: https://codereview.chromium.org/18261008
2013-07-08R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst regTom Stellard
Patch by: Vincent Lejeune https://bugs.freedesktop.org/show_bug.cgi?id=64877 NOTE: This is a candidate for the 3.3 branch. Merged from r182600 Author: Tom Stellard <thomas.stellard@amd.com> Date: Thu May 23 18:26:42 2013 +0000 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@185868 91177308-0d34-0410-b5e6-96231b3b80d8
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