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2013-04-04X86 cost model: Differentiate cost for vector shifts of constantsArnold Schwaighofer
SSE2 has efficient support for shifts by a scalar. My previous change of making shifts expensive did not take this into account marking all shifts as expensive. This would prevent vectorization from happening where it is actually beneficial. With this change we differentiate between shifts of constants and other shifts. radar://13576547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178808 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04CostModel: Add parameter to instruction cost to further classify operand valuesArnold Schwaighofer
On certain architectures we can support efficient vectorized version of instructions if the operand value is uniform (splat) or a constant scalar. An example of this is a vector shift on x86. We can efficiently support for (i = 0 ; i < ; i += 4) w[0:3] = v[0:3] << <2, 2, 2, 2> but not for (i = 0; i < ; i += 4) w[0:3] = v[0:3] << x[0:3] This patch adds a parameter to getArithmeticInstrCost to further qualify operand values as uniform or uniform constant. Targets can then choose to return a different cost for instructions with such operand values. A follow-up commit will test this feature on x86. radar://13576547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178807 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04Rename the current PPC BCL definition to BCLalwaysHal Finkel
BCL is normally a conditional branch-and-link instruction, but has an unconditional form (which is used in the SjLj code, for example). To make clear that this BCL instruction definition is specifically the special unconditional form (which does not meaningfully take a condition-register input), rename it to BCLalways. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178803 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04PPC: Improve code generation for mixed-precision reciprocal sqrtHal Finkel
The DAGCombine logic that recognized a/sqrt(b) and transformed it into a multiplication by the reciprocal sqrt did not handle cases where the sqrt and the division were separated by an fpext or fptrunc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178801 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04Hexagon: Expand br_cc.Jyotsna Verma
It fixes following tests for Hexagon: CodeGen/Generic/2003-07-29-BadConstSbyte.ll CodeGen/Generic/2005-10-21-longlonggtu.ll CodeGen/Generic/2009-04-28-i128-cmp-crash.ll CodeGen/Generic/MachineBranchProb.ll CodeGen/Generic/builtin-expect.ll CodeGen/Generic/pr12507.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178794 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04[XCore] Add bru instruction.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178783 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04[XCore] The RRegs register class is a superset of GRRegs.Richard Osborne
At the time when the XCore backend was added there were some issues with with overlapping register classes but these all seem to be fixed now. Describing the register classes correctly allow us to get rid of a codegen only instruction (LDAWSP_lru6_RRegs) and it means we can disassemble ru6 instructions that use registers above r11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04Avoid high-latency false CPSR dependencies even for tMOVSi.Jakob Stoklund Olesen
The Thumb2SizeReduction pass avoids false CPSR dependencies, except it still aggressively creates tMOVi8 instructions because they are so common. Avoid creating false CPSR dependencies even for tMOVi8 instructions when the the CPSR flags are known to have high latency. This allows integer computation to overlap floating point computations. Also process blocks in a reverse post-order and propagate high-latency flags to successors. <rdar://problem/13468102> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178773 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04R600: Use a mask for offsets when encoding instructionsVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178763 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04R600: Fix wrong address when substituting ENDIFVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178762 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04R600: Take export into account when computing cf addressVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178761 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04Add SPARC v9 support for select on 64-bit compares.Jakob Stoklund Olesen
This requires v9 cmov instructions using the %xcc flags instead of the %icc flags. Still missing: - Select floats on %xcc flags. - Select i64 on %fcc flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178737 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03X86 cost model: Vector shifts are expensive in most casesArnold Schwaighofer
The default logic does not correctly identify costs of casts because they are marked as custom on x86. For some cases, where the shift amount is a scalar we would be able to generate better code. Unfortunately, when this is the case the value (the splat) will get hoisted out of the loop, thereby making it invisible to ISel. radar://13130673 radar://13537826 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178703 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03R600: Fix last ALU of a clause being emitted in a separate clauseVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178675 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Cleanup PPC reciprocal-estimate functionalityHal Finkel
Incorporating review feedback from Bill Schmidt on r178617. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178672 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03R600: Factorize maximum alu per clause in a single locationVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178667 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03R600: Simplify data structure and add DEBUG to R600ControlFlowFinalizerVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178665 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03R600: Consider KILLGT as an ALU instructionVincent Lejeune
Mesa does not override llvm behavior wrt KILLGT anymore so llvm has to handle KILLGT on its own. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178664 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03PPC: Enable FRES and FRSQRTE on the default PPC64 descriptionHal Finkel
I discussed this with Bill Schmidt on IRC, and it was decided that this is a safe and reasonable default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178659 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03PPC: Add a FIXME regarding the non-working fma+fneg Altivec patternHal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178658 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Remove some obsolete PowerPC/README entriesHal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178657 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03More direct types in PowerPC AltiVec intrinsics.Ulrich Weigand
This patch follows up on work done by Bill Schmidt in r178277, and replaces most of the remaining uses of VRRC in ISEL DAG patterns. The resulting .inc files are identical except for comments, so no change in code generation is expected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178656 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Fix PR15632: No support for ppcf128 floating-point remainder on PowerPC.Bill Schmidt
For this we need to use a libcall. Previously LLVM didn't implement libcall support for frem, so I've added it in the usual straightforward manner. A test case from the bug report is included. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178639 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03AArch64: implement ETMv4 trace system registers.Tim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178637 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Fix SRet for thiscall in i686-pc-win32Timur Iskhodzhanov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178634 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03AArch64: switch patterns to be type-based rather than RegClass-basedTim Northover
It's a bit of churn in the blame log, but I think there are real benefits to the newer system so I'm making the change in one go. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178633 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Add 64-bit compare + branch for SPARC v9.Jakob Stoklund Olesen
The same compare instruction is used for 32-bit and 64-bit compares. It sets two different sets of flags: icc and xcc. This patch adds a conditional branch instruction using the xcc flags for 64-bit compares. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178621 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Remove some unsupported-feature comments from PPC.tdHal Finkel
These refer to the reciprocal estimate support recently committed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178618 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Use PPC reciprocal estimates with Newton iteration in fast-math modeHal Finkel
When unsafe FP math operations are enabled, we can use the fre[s] and frsqrte[s] instructions, which generate reciprocal (sqrt) estimates, together with some Newton iteration, in order to quickly generate floating-point division and sqrt results. All of these instructions are separately optional, and so each has its own feature flag (except for the Altivec instructions, which are covered under the existing Altivec flag). Doing this is not only faster than using the IEEE-compliant fdiv/fsqrt instructions, but allows these computations to be pipelined with other computations in order to hide their overall latency. I've also added a couple of missing fnmsub patterns which turned out to be missing (but are necessary for good code generation of the Newton iterations). Altivec needs a similar fix, but that will probably be more complicated because fneg is expanded for Altivec's v4f32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178617 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Formatting.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178589 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02[mips] Small update to the implementation of eh.return for Mips.Akira Hatanaka
This patch initializes t9 to the handler address, but only if the relocation model is pic. This handles the case where handler to which eh.return jumps points to the start of the function. Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178588 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02[mips] Expand pseudo multiply/divide instructions in MipsCodeEmitter.cpp.Akira Hatanaka
This patch fixes the following two tests which have been failing on llvm-mips-linux builder since r178403: LLVM :: Analysis/Profiling/load-branch-weights-ifs.ll LLVM :: Analysis/Profiling/load-branch-weights-loops.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178584 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02[ms-inline asm] Add support for parsing variables with namespace aliasChad Rosier
qualifiers. This patch only adds support for parsing these identifiers in the X86AsmParser. The front-end interface isn't capable of looking up these identifiers at this point in time. The end result is the compiler now errors during object file emission, rather than at parse time. Test case coming shortly. Part of rdar://13499009 and PR13340 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178566 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Fix PR15630: Replace faulty stdcx. with stwcx.Bill Schmidt
When doing a partword atomic operation, a lwarx was being paired with a stdcx. instead of a stwcx. when compiling for a 64-bit target. The target has nothing to do with it in this case; we always need a stwcx. Thanks to Kai Nacke for reporting the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178559 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02[fast-isel] Use the correct API to disable FastLowerArguments for Win64.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178549 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02[NVPTX] Fix a few style issues in NVVMReflectJustin Holewinski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178536 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Add 64-bit load and store instructions.Jakob Stoklund Olesen
There is only a few new instructions, the rest is handled with patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178528 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Basic 64-bit ALU operations.Jakob Stoklund Olesen
SPARC v9 extends all ALU instructions to 64 bits, so we simply need to add patterns to use them for both i32 and i64 values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178527 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Materialize 64-bit immediates.Jakob Stoklund Olesen
The last resort pattern produces 6 instructions, and there are still opportunities for materializing some immediates in fewer instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178526 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Add 64-bit shift instructions.Jakob Stoklund Olesen
SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right instructions are still usable as zero and sign extensions. This adds new F3_Sr and F3_Si instruction formats that probably should be used for the 32-bit shifts as well. They don't really encode an simm13 field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178525 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Add predicates for distinguishing 32-bit and 64-bit modes.Jakob Stoklund Olesen
The 'sparc' architecture produces 32-bit code while 'sparcv9' produces 64-bit code. It is also possible to run 32-bit code using SPARC v9 instructions with: llc -march=sparc -mattr=+v9 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Add support for 64-bit calling convention.Jakob Stoklund Olesen
This is far from complete, but it is enough to make it possible to write test cases using i64 arguments. Missing features: - Floating point arguments. - Receiving arguments on the stack. - Calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178523 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Add an I64Regs register class for 64-bit registers.Jakob Stoklund Olesen
We are going to use the same registers for 32-bit and 64-bit values, but in two different register classes. The I64Regs register class has a larger spill size and alignment. The addition of an i64 register class confuses TableGen's type inference, so it is necessary to clarify the type of some immediates and the G0 register. In 64-bit mode, pointers are i64 and should use the I64Regs register class. Implement getPointerRegClass() to dynamically provide the pointer register class depending on the subtarget. Use ptr_rc and iPTR for memory operands. Finally, add the i64 type to the IntRegs register class. This register class is not used to hold i64 values, I64Regs is for that. The type is required to appease TableGen's type checking in output patterns like this: def : Pat<(add i64:$a, i64:$b), (ADDrr $a, $b)>; SPARC v9 uses the same ADDrr instruction for i32 and i64 additions, and TableGen doesn't know to check the type of register sub-classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178522 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Fix typo in PPCISelLoweringHal Finkel
Thanks to Bill Schmidt for finding this in review of r178480. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178521 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02The divide unit is not pipeline, but it is still buffered.Andrew Trick
Buffered means a later divide may be executed out-of-order while a prior divide is sitting (buffered) in a reservation station. You can tell it's not pipelined, because operations that use it reserve it for more than one cycle: def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> { let Latency = 25; let ResourceCycles = [1, 10]; } We don't currently distinguish between an unpipeline operation and one that is split into multiple micro-ops requiring the same unit. Except that the later may have NumMicroOps > 1 if they also consume issue/dispatch resources. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178519 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01Target/R600: Fix CMake build to add missing files.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178508 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01R600: Add support for native control flowVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178505 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01R600/SI: Share code recording ShaderTypeAttribute between generationsVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178504 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01R600: Emit CF_ALU and use true kcache register.Vincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178503 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01Fix a bad assert in PPCTargetLoweringHal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178489 91177308-0d34-0410-b5e6-96231b3b80d8
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