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2013-04-23[mips] Compare splat value with element size instead of calling isUIntN.Akira Hatanaka
No intended changes in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180130 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23DAGCombine should not aggressively fold SEXT(VSETCC(...)) into a wider ↵Owen Anderson
VSETCC without first checking the target's vector boolean contents. This exposed an issue with PowerPC AltiVec where it appears it was setting the wrong vector boolean contents. The included change fixes the PowerPC tests, and was OK'd by Hal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180129 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23R600: Use .AMDGPU.config section to emit stacksizeVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180124 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23R600: Add CF_ENDVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23Hexagon: Remove duplicate instructions to handle global/immediate valuesJyotsna Verma
for absolute/absolute-set addressing modes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180120 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23AArch64: remove unnecessary check that RS is validTim Northover
AArch64 always demands a register-scavenger, so the pointer should never be NULL. However, in the spirit of paranoia, we'll assert it before use just in case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180080 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22Remove unused DwarfSectionOffsetDirective stringMatt Arsenault
The value isn't actually used, and setting it emits a COFF specific directive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180064 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22Move C++ code out of the C headers and into either C++ headersEric Christopher
or the C++ files themselves. This enables people to use just a C compiler to interoperate with LLVM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180063 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22[ms-inline asm] Removed this unnecessary check. In the current implementation,Chad Rosier
Disp will always be one of MCSymbolRefExpr or MCConstantExpr, and never NULL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180059 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22[ms-inline asm] Add the OpDecl to the InlineAsmIdentifierInfo struct and in turnChad Rosier
the MCParsedAsmOperand. Part of rdar://13663589 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180054 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22Fix unused variable warning.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180044 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-2280 columns.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180040 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22[mips] In performDSPShiftCombine, check that all elements in the vector areAkira Hatanaka
shifted by the same amount and the shift amount is smaller than the element size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180039 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22[ms-inline asm] Remove the identifier parsing logic from the AsmParser. This isChad Rosier
now taken care of by the frontend, which allows us to parse arbitrary C/C++ variables. Part of rdar://13663589 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180037 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22[ms-inline asm] Refactor/clean up the SemaLookup interface. No functionalChad Rosier
change indended. Part of rdar://13663589 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180028 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22No really, don't store anything to this since it's unconditionallyEric Christopher
set below. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180015 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22Remove variable store that is never read.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180014 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22Fix for 5.5 Parameter Passing --> Stage C:Stepan Dyatkovskiy
-- C.4 and C.5 statements, when NSAA is not equal to SP. -- C.1.cp statement for VA functions. Note: There are no VFP CPRCs in a variadic procedure. Before this patch "NSAA != 0" means "don't use GPRs anymore ". But there are some exceptions in AAPCS. 1. For non VA function: allocate all VFP regs for CPRC. When all VFPs are allocated CPRCs would be sent to stack, while non CPRCs may be still allocated in GRPs. 2. Check that for VA functions all params uses GPRs and then stack. No exceptions, no CPRCs here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180011 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-21Legalize vector truncates by parts rather than just splitting.Jim Grosbach
Rather than just splitting the input type and hoping for the best, apply a bit more cleverness. Just splitting the types until the source is legal often leads to an illegal result time, which is then widened and a scalarization step is introduced which leads to truly horrible code generation. With the loop vectorizer, these sorts of operations are much more common, and so it's worth extra effort to do them well. Add a legalization hook for the operands of a TRUNCATE node, which will be encountered after the result type has been legalized, but if the operand type is still illegal. If simple splitting of both types ends up with the result type of each half still being legal, just do that (v16i16 -> v16i8 on ARM, for example). If, however, that would result in an illegal result type (v8i32 -> v8i8 on ARM, for example), we can get more clever with power-two vectors. Specifically, split the input type, but also widen the result element size, then concatenate the halves and truncate again. For example on ARM, To perform a "%res = v8i8 trunc v8i32 %in" we transform to: %inlo = v4i32 extract_subvector %in, 0 %inhi = v4i32 extract_subvector %in, 4 %lo16 = v4i16 trunc v4i32 %inlo %hi16 = v4i16 trunc v4i32 %inhi %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16 %res = v8i8 trunc v8i16 %in16 This allows instruction selection to generate three VMOVN instructions instead of a sequences of moves, stores and loads. Update the ARMTargetTransformInfo to take this improved legalization into account. Consider the simplified IR: define <16 x i8> @test1(<16 x i32>* %ap) { %a = load <16 x i32>* %ap %tmp = trunc <16 x i32> %a to <16 x i8> ret <16 x i8> %tmp } define <8 x i8> @test2(<8 x i32>* %ap) { %a = load <8 x i32>* %ap %tmp = trunc <8 x i32> %a to <8 x i8> ret <8 x i8> %tmp } Previously, we would generate the truly hideous: .syntax unified .section __TEXT,__text,regular,pure_instructions .globl _test1 .align 2 _test1: @ @test1 @ BB#0: push {r7} mov r7, sp sub sp, sp, #20 bic sp, sp, #7 add r1, r0, #48 add r2, r0, #32 vld1.64 {d24, d25}, [r0:128] vld1.64 {d16, d17}, [r1:128] vld1.64 {d18, d19}, [r2:128] add r1, r0, #16 vmovn.i32 d22, q8 vld1.64 {d16, d17}, [r1:128] vmovn.i32 d20, q9 vmovn.i32 d18, q12 vmov.u16 r0, d22[3] strb r0, [sp, #15] vmov.u16 r0, d22[2] strb r0, [sp, #14] vmov.u16 r0, d22[1] strb r0, [sp, #13] vmov.u16 r0, d22[0] vmovn.i32 d16, q8 strb r0, [sp, #12] vmov.u16 r0, d20[3] strb r0, [sp, #11] vmov.u16 r0, d20[2] strb r0, [sp, #10] vmov.u16 r0, d20[1] strb r0, [sp, #9] vmov.u16 r0, d20[0] strb r0, [sp, #8] vmov.u16 r0, d18[3] strb r0, [sp, #3] vmov.u16 r0, d18[2] strb r0, [sp, #2] vmov.u16 r0, d18[1] strb r0, [sp, #1] vmov.u16 r0, d18[0] strb r0, [sp] vmov.u16 r0, d16[3] strb r0, [sp, #7] vmov.u16 r0, d16[2] strb r0, [sp, #6] vmov.u16 r0, d16[1] strb r0, [sp, #5] vmov.u16 r0, d16[0] strb r0, [sp, #4] vldmia sp, {d16, d17} vmov r0, r1, d16 vmov r2, r3, d17 mov sp, r7 pop {r7} bx lr .globl _test2 .align 2 _test2: @ @test2 @ BB#0: push {r7} mov r7, sp sub sp, sp, #12 bic sp, sp, #7 vld1.64 {d16, d17}, [r0:128] add r0, r0, #16 vld1.64 {d20, d21}, [r0:128] vmovn.i32 d18, q8 vmov.u16 r0, d18[3] vmovn.i32 d16, q10 strb r0, [sp, #3] vmov.u16 r0, d18[2] strb r0, [sp, #2] vmov.u16 r0, d18[1] strb r0, [sp, #1] vmov.u16 r0, d18[0] strb r0, [sp] vmov.u16 r0, d16[3] strb r0, [sp, #7] vmov.u16 r0, d16[2] strb r0, [sp, #6] vmov.u16 r0, d16[1] strb r0, [sp, #5] vmov.u16 r0, d16[0] strb r0, [sp, #4] ldm sp, {r0, r1} mov sp, r7 pop {r7} bx lr Now, however, we generate the much more straightforward: .syntax unified .section __TEXT,__text,regular,pure_instructions .globl _test1 .align 2 _test1: @ @test1 @ BB#0: add r1, r0, #48 add r2, r0, #32 vld1.64 {d20, d21}, [r0:128] vld1.64 {d16, d17}, [r1:128] add r1, r0, #16 vld1.64 {d18, d19}, [r2:128] vld1.64 {d22, d23}, [r1:128] vmovn.i32 d17, q8 vmovn.i32 d16, q9 vmovn.i32 d18, q10 vmovn.i32 d19, q11 vmovn.i16 d17, q8 vmovn.i16 d16, q9 vmov r0, r1, d16 vmov r2, r3, d17 bx lr .globl _test2 .align 2 _test2: @ @test2 @ BB#0: vld1.64 {d16, d17}, [r0:128] add r0, r0, #16 vld1.64 {d18, d19}, [r0:128] vmovn.i32 d16, q8 vmovn.i32 d17, q9 vmovn.i16 d16, q8 vmov r0, r1, d16 bx lr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179989 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-21Passing arguments to varags functions under the SPARC v9 ABI.Jakob Stoklund Olesen
Arguments after the fixed arguments never use the floating point registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179987 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-21Fix the SETHIimm pattern for 64-bit code.Jakob Stoklund Olesen
Don't ignore the high 32 bits of the immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179985 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-21ARM: Use ldrd/strd to spill 64-bit pairs when available.Tim Northover
This allows common sp-offsets to be part of the instruction and is probably faster on modern CPUs too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179977 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-20Compile varargs functions for SPARCv9.Jakob Stoklund Olesen
With a little help from the frontend, it looks like the standard va_* intrinsics can do the job. Also clean up an old bitcast hack in LowerVAARG that dealt with unaligned double loads. Load SDNodes can specify an alignment now. Still missing: Calling varargs functions with float arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179961 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-20ARM: don't add FrameIndex offset for LDMIA (has no immediate)Tim Northover
Previously, when spilling 64-bit paired registers, an LDMIA with both a FrameIndex and an offset was produced. This kind of instruction shouldn't exist, and the extra operand was being confused with the predicate, causing aborts later on. This removes the invalid 0-offset from the instruction being produced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179956 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-20AArch64: remove useless commentTim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179952 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-20Remove unused ShouldFoldAtomicFences flag.Tim Northover
I think it's almost impossible to fold atomic fences profitably under LLVM/C++11 semantics. As a result, this is now unused and just cluttering up the target interface. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179940 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-20Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.Tim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-20Move PPC getSwappedPredicate for reuseHal Finkel
The getSwappedPredicate function can be used in other places (such as in improvements to the PPCCTRLoops pass). Instead of trapping it as a static function in PPCInstrInfo, move it into PPCPredicates with other predicate-related things. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179926 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-20Add CodeGen support for functions that always return arguments via a new ↵Stephen Lin
parameter attribute 'returned', which is taken advantage of in target-independent tail call opportunity detection and in ARM call lowering (when placed on an integral first parameter). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179925 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-20Test commitStephen Lin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179913 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[mips] Instruction selection patterns for DSP-ASE vector shifts.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179906 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Move TryToFoldFastISelLoad to FastISel, where it belongs. In general, I'mEli Bendersky
trying to move as much FastISel logic as possible out of the main path in SelectionDAGISel - intermixing them just adds confusion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179902 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19ArrayRefize getMachineNode(). No functionality change.Michael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Fix PPC optimizeCompareInstr swapped-sub argument handlingHal Finkel
When matching a compare with a subtract where the arguments of the compare are swapped w.r.t. the arguments of the subtract, we need to negate the predicates (or CR bit indices) of the users. This, however, is not the same as inverting the predicate (negating LT -> GT, but inverting LT -> GE, for example). The ARM backend seems to do this correctly, but when I adapted the code for the PPC backend, I introduced an error in this logic. Comparison optimization is now enabled again by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179899 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Do not mangle in MS-way the globals with magic \001 in the name.Anton Korobeynikov
Based on the patch by David Nadlinger! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179889 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Make code layout more canonical with iniline asm handled last.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179875 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[mips] First patch which adds support for micromips.Akira Hatanaka
This patch adds support for recoded (meaning assembly-language compatible to standard mips32) arithmetic 32-bit instructions. Patch by Zoran Jovanovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179873 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[mips] Fix InstAlias of XOR and OR macros. Set EmitAlias flag and changeAkira Hatanaka
operand type to uimm16. Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179872 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Refactor the parsing of identifiers. No functional changeChad Rosier
indended. Part of rdar://13663589 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179871 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Remove these asserts. C++ variables that use namespaceChad Rosier
qualifiers don't necessarily begin with an identifier (e.g., ::foo::bar). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179867 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Move this variable into the scope in which it is used.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179866 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Make this a hard error.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179865 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Cleanup the dot operator implementation.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179856 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19ARM: Permit "sp" in ARM variant of STREXD instructionsTim Northover
Patch from Mihail Popa git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179854 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19ARM: permit "sp" in ARM variants of MOVW/MOVT instructionsTim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179847 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Use 'array_lengthof' as possible to avoid magic numbersMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179833 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19R600: Add pattern for the BFI_INT instructionTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179830 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19R600/SI: Use InstFlag for VOP3 modifier operandsTom Stellard
InstFlag has a default value of 0 and will simplify the VOP3 patterns. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179829 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Use an enum instead of magic constants to improve readability.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179820 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18[ms-inline asm] Apply the condition code mnemonic aliases to both the Intel andChad Rosier
AT&T dialect. Test case for r179804 as well. rdar://13674398 and PR13340. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179813 91177308-0d34-0410-b5e6-96231b3b80d8
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