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2012-03-21Put Is64BitMemOperand into !defined(NDEBUG) for now.Joerg Sonnenberger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153185 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21Use a signed value for this enum to avoid spuriuos warnings from gcc.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153184 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21Fix generation of the address size override prefix. Add assertions forJoerg Sonnenberger
the invalid cases. At least 16bit operand in 64bit mode is currently not rejected in the parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153166 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21Spacing fixes and using 'unsigned' instead of 'int' to index to select ↵Craig Topper
shuffle elements for consistency with other shuffle code in X86 backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153154 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20[avx] Add patterns for combining vextractf128 + vmovaps/vmovups/vmobdqu toChad Rosier
vextractf128 with 128-bit mem dest. Combines vextractf128 $0, %ymm0, %xmm0 vmovaps %xmm0, (%rdi) to vextractf128 $0, %ymm0, (%rdi) rdar://11082570 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153139 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20[avx] Add the AddedComplexity to the VINSERTI128 avx2 patterns to giveChad Rosier
precedence over the VINSERTF128 avx1 patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153114 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Whitespace.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153105 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20[avx] Move the vextractf128 patterns closer to the vextractf128 def. RemoveChad Rosier
whitespace from test case. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153103 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20[avx] Adjust the VINSERTF128rm pattern to allow for unaligned loads.Chad Rosier
This results in things such as vmovups 16(%rdi), %xmm0 vinsertf128 $1, %xmm0, %ymm0, %ymm0 to be combined to vinsertf128 $1, 16(%rdi), %ymm0, %ymm0 rdar://11076953 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153092 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Remove code that prevented lowering shuffles if they are used by load and ↵Craig Topper
themselves used by a extract_vector_elt. This was done to allow the DAG combiner to collapse to a single element load. Unfortunately, sometimes the extract_vector_elt would disappear before DAG combine could do the transformation leaving a vector_shuffle that isel couldn't handle. New code lets the shuffle be converted to a target specific node, but then adds a combine routine that can convert target specific nodes back to vector_shuffles if the folding criteria are met. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153080 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Factor out target shuffle mask decoding from getShuffleScalarElt and use a ↵Craig Topper
SmallVector of int instead of unsigned for shuffle mask in decode functions. Preparation for another change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153079 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19This patch adds X86 instruction itineraries for non-pseudo opcodes inPreston Gurd
X86InstrCompiler.td. It also adds –mcpu-generic to the legalize-shift-64.ll test so the test will pass if run on an Intel Atom CPU, which would otherwise produce an instruction schedule which differs from that which the test expects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153033 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19Add a note for -ffast-math optimization of vector norm.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153031 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-18isCommutedMOVLMask should only look at 128-bit vectors to match isMOVLMask.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper
some superfluous forward declarations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15[avx] Add patterns for VINSERTF128rm.Chad Rosier
This results in things such as vmovaps -96(%rbx), %xmm1 vinsertf128 $1, %xmm1, %ymm0, %ymm0 to be combined to vinsertf128 $1, -96(%rbx), %ymm0, %ymm0 rdar://10643481 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152762 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13Change the X86 assembler to not require a segment register on stringKevin Enderby
instruction's destination operand like it does for the source operand. Also fix a typo in the comment for X86AsmParser::isSrcOp(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152654 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-12Added a missing error check for X86 assembly with mismatched base and indexKevin Enderby
registers not both being 64-bit or both being 32-bit registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152580 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-11Convert more static tables of registers used by calling convention to ↵Craig Topper
uint16_t to reduce space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152538 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10*fix typo in comment; test of commit accessKay Tiong Khoo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152507 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10C files in llvm still have to be C89 compliant, remove C++-style comments.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152495 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10Fix disasm of iret, sysexit, and sysret when displayed with Intel syntax.Bill Wendling
Patch by Kay Tiong Khoo! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152487 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09Add the missing call to Error when a bad X86 scale expression is parsed.Kevin Enderby
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152443 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09Fix the x86 disassembler to at least print the lock prefix if it is the firstKevin Enderby
prefix. Added a FIXME to remind us this still does not work when it is not the first prefix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152414 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09Use uint16_t to store opcodes in static tables in X86 backend.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152391 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09Fix a regression from r147481.Chad Rosier
Original commit message from r147481: DAGCombine for transforming 128->256 casts into a vmovaps, rather then a vxorps + vinsertf128 pair if the original vector came from a load. Fix: Unaligned loads need to generate a vmovups. rdar://10974078 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152366 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Fix the operand ordering on aliases for shld and shrd. PR12173, part 2.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152136 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05Make MCRegisterInfo available to the the MCInstPrinter.Jim Grosbach
Used to allow context sensitive printing of super-register or sub-register references. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152043 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05Address Evan's comments for r151877.Chad Rosier
Specifically, remove the magic number when checking to see if the copy has a glue operand and simplify the checking logic. rdar://10930395 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152041 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05Make aliases for shld and shrd match gas. PR12173.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152014 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04Use uint16_t to store register overlaps to reduce static data.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper
size of static data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04Use uint8_t instead of enums to store values in X86 disassembler table. ↵Craig Topper
Shaves 150k off the size of X86DisassemblerDecoder.o git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151995 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-02Prevent obscure and incorrect tail-call optimization.Chad Rosier
In this instance we are generating the tail-call during legalizeDAG. The 2nd floor call can't be a tail call because it clobbers %xmm1, which is defined by the first floor call. The first floor call can't be a tail-call because it's not in the tail position. The only reasonable way I could think to fix this in a target-independent manner was to check for glue logic on the copy reg. rdar://10930395 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151877 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Minimal changes for LLVM to compile under VS11.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151849 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29Added annotations for x86 pc relative loads to llvm's 'C' disassembler.Kevin Enderby
So with darwin's otool(1) an x86_64 hello world .o file will print: leaq L_.str(%rip), %rax ## literal pool for: Hello world git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151769 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29Intel Atom instruction itineraries for mov sign extension and mov zero ↵Andrew Trick
extension. Patch by Tyler Nowicki! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151743 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29Make MemoryObject accessor members const againDerek Schuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151687 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Re-commit r151623 with fix. Only issue special no-return calls if it's a ↵Evan Cheng
direct call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar
prediction. ...", it is breaking the Clang build during the Compiler-RT part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng
the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27This patch adds instruction latencies for the SSE instructionsPreston Gurd
to the instruction scheduler for the Intel Atom. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151590 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27Add q suffix aliases for the fistp and fisttp mnemonics.Chad Rosier
rdar://10921670 PR11935 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151543 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by ↵Craig Topper
Kay Tiong Khoo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151510 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-25Target/X86: Fix assertion failures and warnings caused by r151382 _ftol2 ↵NAKAMURA Takumi
lowering for i386-*-win32 targets. Patch by Joe Groff. [Joe Groff] Hi everyone. My previous patch applied as r151382 had a few problems: Clang raised a warning, and X86 LowerOperation would assert out for fptoui f64 to i32 because it improperly lowered to an illegal BUILD_PAIR. Here's a patch that addresses these issues. Let me know if any other changes are necessary. Thanks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151432 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24Add WIN_FTOL_* psudo-instructions to model the unique calling conventionMichael J. Spencer
used by the Win32 _ftol2 runtime function. Patch by Joe Groff! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151382 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24Turn avx insert intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove ↵Pete Cooper
duplicate patterns for selecting the intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151342 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23Updated the llvm-mc disassembler C API to support for the X86 target.Kevin Enderby
rdar://10873652 As part of this I updated the llvm-mc disassembler C API to always call the SymbolLookUp call back even if there is no getOpInfo call back. If there is a getOpInfo call back that is tried first and then if that gets no information then the SymbolLookUp is called. I also made the code more robust by memset(3)'ing to zero the LLVMOpInfo1 struct before then setting SymbolicOp.Value before for the call to getOpInfo. And also don't use any values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't use any of the ReferenceType or ReferenceName values from SymbolLookUp if it returns NULL. rdar://10873563 and rdar://10873683 For the X86 target also fixed bugs so the annotations get printed. Also fixed a few places in the ARM target that was not producing symbolic operands for some instructions. rdar://10878166 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151267 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22Properly emit _fltused with FastISel. Refactor to share code with SDAG.Michael J. Spencer
Patch by Joe Groff! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151183 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22Remove extra semi-colons.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151169 91177308-0d34-0410-b5e6-96231b3b80d8
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