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2013-05-06[SystemZ] Add back endUlrich Weigand
This adds the actual lib/Target/SystemZ target files necessary to implement the SystemZ target. Note that at this point, the target cannot yet be built since the configure bits are missing. Those will be provided shortly by a follow-on patch. This version of the patch incorporates feedback from reviews by Chris Lattner and Anton Korobeynikov. Thanks to all reviewers! Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181203 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24Remove the SystemZ backend.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21fix a long standing wart: all the ComplexPattern's were beingChris Lattner
passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-04zap dead code.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113073 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28Merge the SystemZ subreg_even32 SubRegIndex into subreg_32bit. The SubRegIndicesJakob Stoklund Olesen
were overspecified when inheriting sub-subregisters, for instance: R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit. This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105063 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25Use enums instead of literals for SystemZ subregistersJakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104612 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17Use const qualifiers with TargetLowering. This eliminates severalDan Gohman
const_casts, and it reinforces the design of the Target classes being immutable. SelectionDAGISel::IsLegalToFold is now a static member function, because PIC16 uses it in an unconventional way. There is more room for API cleanup here. And PIC16's AsmPrinter no longer uses TargetLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02Sink InstructionSelect() out of each target into SDISel, and rename itChris Lattner
DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader. Sink some other stuff out of DAGISelHeader into SDISel. Eliminate the various 'Indent' stuff from various targets, which dates to when isel was recursive. 17 files changed, 114 insertions(+), 430 deletions(-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97555 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-15Split SelectionDAGISel::IsLegalAndProfitableToFold toEvan Cheng
IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use. This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96255 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-09move target-independent opcodes out of TargetInstrInfoChris Lattner
into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-05Change SelectCode's argument from SDValue to SDNode *, to make it moreDan Gohman
clear what information these functions are actually using. This is also a micro-optimization, as passing a SDNode * around is simpler than passing a { SDNode *, int } by value or reference. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92564 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-04Fix invalid chain folding for memory variant of sdiv / udivAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92472 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-05Remove uninteresting and confusing debug output.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86149 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25Rename getTargetNode to getMachineNode, for consistency with theDan Gohman
naming scheme used in SelectionDAG, where there are multiple kinds of "target" nodes, but "machine" nodes are nodes which represent a MachineInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82790 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-23Fix some refactos for iostream changes (in -Asserts mode).Daniel Dunbar
- The world needs better C++ refactoring tools, can I get an Amen!? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79843 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-23eliminate uses of cerr()Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79834 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-23eliminate the last DOUTs from the targets.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79833 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson
while the latter is capable of representing either a primitive or an extended type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson
own struct type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-17Fix 'may be used uninitialized' warning.Daniel Dunbar
- Anton, please review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76144 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16UnbreakAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76064 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Fix logic inversion for RI-mode address selectionAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76052 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Unbreak mvi and friends - emit only 'significant' part of the operandAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76041 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Provide consistent subreg idx scheme. This (hopefully) fixes remaining ↵Anton Korobeynikov
divide problems git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76011 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Use divide single for 32 bit signed dividesAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76010 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Remove redundand register moveAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76004 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Properly handle divides. As a bonus - implement memory versions of them.Anton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76003 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-1632 bit shifts have only 12 bit displacementsAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76000 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16TyposAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75991 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Consolidate reg-imm / reg-reg-imm address mode selection logic in one place.Anton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75990 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Add support for 12 bit displacementsAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75988 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-1632-bit ri addressing mode has only 12-bit displacementAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75973 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Swap the order of imm and idx field for rri addrmode in order to make ↵Anton Korobeynikov
handling of rri and ri addrmodes common git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75937 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Do not truncate sign bits for negative immsAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75936 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Add address computation stuffAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75935 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Add stores and truncstoresAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75931 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Add patterns for various extloadsAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75930 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Do some heroic rri address matching (shamelessly stolen from x86 backend). ↵Anton Korobeynikov
Not tested though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75929 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Add shifts and reg-imm address matchingAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75927 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Add bunch of reg-imm movsAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75921 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Provide masked reg-imm 'or' and 'and'Anton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75919 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16Let's start another backend :)Anton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75909 91177308-0d34-0410-b5e6-96231b3b80d8
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