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passed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22886 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22837 91177308-0d34-0410-b5e6-96231b3b80d8
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Only run createLowerConstantExpressionsPass for the simple isel. The DAG
isel has no need for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22794 91177308-0d34-0410-b5e6-96231b3b80d8
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back once a DAG->DAG ISel exists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22778 91177308-0d34-0410-b5e6-96231b3b80d8
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depending on the command line option. Now the command line option just
sets the subtarget as appropriate. G5 opts will now default to on on
G5-enabled nightly testers among other machines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22688 91177308-0d34-0410-b5e6-96231b3b80d8
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a subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22677 91177308-0d34-0410-b5e6-96231b3b80d8
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and asm printer for PowerPC if one is not specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22659 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22644 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22523 91177308-0d34-0410-b5e6-96231b3b80d8
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Remove the LoadHiAddr pseudo-instruction.
Optimization of stores to and loads from statics.
Force JIT to use new non-PIC codepaths.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22494 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22493 91177308-0d34-0410-b5e6-96231b3b80d8
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8-byte align doubles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22486 91177308-0d34-0410-b5e6-96231b3b80d8
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automatically generated from a target description.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22470 91177308-0d34-0410-b5e6-96231b3b80d8
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interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22282 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21425 91177308-0d34-0410-b5e6-96231b3b80d8
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Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
0 == off
1 == on
2 == target default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21309 91177308-0d34-0410-b5e6-96231b3b80d8
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Add initial (buggy) implementation of 64 bit pattern ISel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21096 91177308-0d34-0410-b5e6-96231b3b80d8
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1) dynamic stack alloc
2) loads
3) shifts
4) subtract
5) immediate form of add, and, or, xor
6) change flag from -pattern-isel to -enable-ppc-pattern-isel
Remove dead arguments from getGlobalBaseReg in the simple ISel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20810 91177308-0d34-0410-b5e6-96231b3b80d8
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be brought up to parity with the current simple ISel in the coming days.
Currently, -pattern-isel is required to trigger it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20805 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20410 91177308-0d34-0410-b5e6-96231b3b80d8
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Loop Strength Reduction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20399 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18830 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18311 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18228 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18159 91177308-0d34-0410-b5e6-96231b3b80d8
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the JIT is made to work!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18155 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18152 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18140 91177308-0d34-0410-b5e6-96231b3b80d8
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or 64-bit mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18038 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17230 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16873 91177308-0d34-0410-b5e6-96231b3b80d8
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32 and 64 bit AsmWriters unified
Darwin and AIX specific features of AsmWriter split out
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16163 91177308-0d34-0410-b5e6-96231b3b80d8
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Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16137 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15955 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15929 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15857 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15746 91177308-0d34-0410-b5e6-96231b3b80d8
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SparcV9 and PowerPC64 without target triples, since they are both 64-bit
big-endian targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15688 91177308-0d34-0410-b5e6-96231b3b80d8
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* Mark InstrInfo with 32 vs. 64 bit flag
* Enable the 64-bit isel and asm printer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15672 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15663 91177308-0d34-0410-b5e6-96231b3b80d8
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printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15662 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15636 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15599 91177308-0d34-0410-b5e6-96231b3b80d8
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Use a PowerPC specific prolog epilog inserter to control where spilled
callee save regs are placed on the stack.
Get rid of implicit return address stack slot, save return address reg
(LR) in appropriate slot
Improve code generated for functions that don't have calls or access
globals
Note from Chris: PowerPCPEI will eventually be eliminated, once the
functionality is merged into CodeGen/PrologEpilogInserter.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15536 91177308-0d34-0410-b5e6-96231b3b80d8
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Patch by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15285 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15122 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15048 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15034 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14911 91177308-0d34-0410-b5e6-96231b3b80d8
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PointerSize)
has been eliminated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14891 91177308-0d34-0410-b5e6-96231b3b80d8
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