| Age | Commit message (Expand) | Author |
|---|
| 2013-05-06 | Print IR from Hexagon MI passes with -print-before/after-all. | Krzysztof Parzyszek |
| 2013-05-06 | Cleanup of the HexagonTargetMachine setup. | Krzysztof Parzyszek |
| 2013-05-06 | Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. | Jyotsna Verma |
| 2013-05-06 | Make references to HexagonTargetMachine "const". | Krzysztof Parzyszek |
| 2013-05-04 | Use consistent function names. | Krzysztof Parzyszek |
| 2013-05-03 | Fix missing include in Hexagon code for Release+Asserts | Reid Kleckner |
| 2013-05-02 | reverting r180953 | Jyotsna Verma |
| 2013-05-02 | Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. | Jyotsna Verma |
| 2013-05-02 | Hexagon - Add peephole optimizations for zero extends. | Pranav Bhandarkar |
| 2013-05-02 | Hexagon: Honor __builtin_expect by using branch probabilities. | Jyotsna Verma |
| 2013-05-01 | Hexagon: Use multiclass for Jump instructions. | Jyotsna Verma |
| 2013-05-01 | Hexagon: Clear isKill flag on the predicate register in | Jyotsna Verma |
| 2013-04-23 | Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions. | Jyotsna Verma |
| 2013-04-23 | Hexagon: Define relations for GP-relative instructions. | Jyotsna Verma |
| 2013-04-23 | Hexagon: Remove assembler mapped instruction definitions. | Jyotsna Verma |
| 2013-04-23 | Hexagon: Remove duplicate instructions to handle global/immediate values | Jyotsna Verma |
| 2013-04-20 | Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE. | Tim Northover |
| 2013-04-19 | ArrayRefize getMachineNode(). No functionality change. | Michael Liao |
| 2013-04-12 | Hexagon: Set isPredicatedNew flag on predicate new instructions. | Jyotsna Verma |
| 2013-04-12 | Hexagon: Set isPredicatedFlase flag for all the instructions with negated pre... | Jyotsna Verma |
| 2013-04-04 | Hexagon: Expand br_cc. | Jyotsna Verma |
| 2013-04-01 | Remove unused typedef. | Duncan Sands |
| 2013-03-31 | There is no longer any need to silence this compiler warning as the warning has | Duncan Sands |
| 2013-03-29 | Hexagon: Add emitFrameIndexDebugValue function to emit debug information. | Jyotsna Verma |
| 2013-03-29 | Hexagon: Disable DwarfUsesInlineInfoSection flag. | Jyotsna Verma |
| 2013-03-28 | Hexagon: Replace switch-case in isDotNewInst with TSFlags. | Jyotsna Verma |
| 2013-03-28 | Hexagon: Enable SupportDebugInfomation and DwarfInSection flags. | Jyotsna Verma |
| 2013-03-28 | Hexagon: Use multiclass for gp-relative instructions. | Jyotsna Verma |
| 2013-03-27 | Switch to LLVM support function abs64 to keep VS2008 happy. | Tim Northover |
| 2013-03-27 | Hexagon: Disable optimizations at O0. | Jyotsna Verma |
| 2013-03-26 | Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth. | Jyotsna Verma |
| 2013-03-26 | Hexagon: Remove HexagonMCInst.h file. It has been replaced with MCTargetDesc/... | Jyotsna Verma |
| 2013-03-22 | Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and w... | Jyotsna Verma |
| 2013-03-14 | Hexagon: Removed asserts regarding alignment and offset. | Jyotsna Verma |
| 2013-03-10 | Cleanup #includes. | Jakub Staszak |
| 2013-03-08 | DAGCombiner: Use correct value type for checking legality of BR_CC v3 | Tom Stellard |
| 2013-03-08 | Hexagon: Add patterns for zero extended loads from i1->i64. | Jyotsna Verma |
| 2013-03-07 | Hexagon: Handle i8, i16 and i1 Var Args. | Jyotsna Verma |
| 2013-03-07 | Hexagon: Add support to lower block address. | Jyotsna Verma |
| 2013-03-05 | reverting patch 176508. | Jyotsna Verma |
| 2013-03-05 | Hexagon: Add support for lowering block address. | Jyotsna Verma |
| 2013-03-05 | Hexagon: Expand addc, adde, subc and sube. | Jyotsna Verma |
| 2013-03-05 | Hexagon: Use MO operand flags to mark constant extended instructions. | Jyotsna Verma |
| 2013-03-05 | Hexagon: Add encoding bits to the TFR64 instructions. | Jyotsna Verma |
| 2013-03-02 | Added FIXME for future Hexagon cleanup. | Andrew Trick |
| 2013-03-01 | Hexagon: Add constant extender support framework. | Jyotsna Verma |
| 2013-02-22 | Remove code copied from GenRegisterInfo.inc. | Andrew Trick |
| 2013-02-21 | Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo | Eli Bendersky |
| 2013-02-21 | Hexagon: Expand cttz, ctlz, and ctpop for now. | Anshuman Dasgupta |
| 2013-02-20 | Update TargetLowering ivars for name policy. | Jim Grosbach |
