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2012-11-27[arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier
classes. Also a bit of cleanup. rdar://12719844 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168728 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27Merge commit '8d20b5f9ff609e70fae5c865931ab0f29e639d9c'Derek Schuff
Conflicts: lib/CodeGen/AsmPrinter/DwarfDebug.cpp lib/CodeGen/AsmPrinter/DwarfDebug.h lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp lib/Target/Mips/MipsISelDAGToDAG.cpp lib/Target/Mips/MipsInstrFPU.td lib/Target/Mips/MipsSubtarget.cpp lib/Target/Mips/MipsSubtarget.h lib/Target/X86/X86MCInstLower.cpp tools/Makefile tools/llc/llc.cpp
2012-11-27[arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier
classes. The associated test case still doesn't pass, but it does have far fewer issues. rdar://12719844 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168657 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-26Fix previous CL to actually work on NaCl (and not only fix non-NaCl).Eli Bendersky
std::min has to be std::max, and the alignment should not be conditioned on hasRawTextSupport BUG= http://code.google.com/p/nativeclient/issues/detail?id=1711 Review URL: https://codereview.chromium.org/11280172
2012-11-26Force function entry alignment only for NaClEli Bendersky
BUG= https://code.google.com/p/nativeclient/issues/detail?id=1711 Review URL: https://codereview.chromium.org/11418159
2012-11-26Decouple MCInstBuilder from the streamer per Eli's request.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168597 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-26Add MCInstBuilder, a utility class to simplify MCInst creation similar to ↵Benjamin Kramer
MachineInstrBuilder. Simplify some repetitive code with it. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168587 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-24ARM: Share applyFixup between ELF and Darwin.Benjamin Kramer
The implementations already diverged a bit, merge them back together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168542 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-20Push/pop and other calling convention lowering conditionalizedDavid Sehr
A number of calling convention related changes were made unconditionally. This makes these conditionalized, although there are still some small differences I would like to address separately in the logs for struct_byval.ll BUG= http://code.google.com/p/nativeclient/issues/detail?id=1711 Review URL: https://codereview.chromium.org/11416053
2012-11-20Remove unnecessary LOCALMOD from ARMMCTargetDesc.cppEli Bendersky
BUG=2751 Review URL: https://codereview.chromium.org/11348164
2012-11-17Mark FP_EXTEND form v2f32 to v2f64 as "expand" for ARM NEON. Patch by Pete ↵Eli Friedman
Couperus. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168240 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-17Rename methods like PairSRegs() to createSRegpairNode() to meet our codingWeiming Zhao
style requirement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168229 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16Remove hard coded registers in ARM ldrexd and strexd instructionsWeiming Zhao
This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168207 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16Make sure FABS on v2f32 and v4f32 is legal on ARM NEONAnton Korobeynikov
This fixes PR14359 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168200 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16Control LSDA only on native clientDavid Sehr
This does not fix any known issue, but the code in question clearly should have been conditional. BUG= http://code.google.com/p/nativeclient/issues/detail?id=1711 Review URL: https://codereview.chromium.org/11417033
2012-11-15Revert the LOCALMOD that disables the NEON feature for Cortex-A8.Eli Bendersky
Since NEON sandboxing in LLVM is now enabled, correctly sandboxed code will be generated during translation. Ran `pnacl/test.sh test-all` manually BUG=3124 Review URL: https://codereview.chromium.org/11415021
2012-11-15Fix AddrIndex for some instructions to be more precise, following Jan's commentsEli Bendersky
BUG=3124 Review URL: https://codereview.chromium.org/11412019
2012-11-15Mark FP_ROUND for converting NEON v2f64 to v2f32 as expand. Add a missingEli Friedman
case to vector legalization so this actually works. Patch by Pete Couperus. Fixes PR12540. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168107 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Sandboxing of VLD instructionsEli Bendersky
BUG=nativeclient:3124 Review URL: https://codereview.chromium.org/11413019
2012-11-15Merge commit '08e9cb46feb0c8e08e3d309a0f9fd75a04ca54fb'Derek Schuff
(svn r167699, also the 3.2 branch point) Conflicts: lib/Target/X86/X86Subtarget.cpp
2012-11-15Use empty parens for empty function parameter list instead of '(void)'.Dmitri Gribenko
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168049 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Revert changing FNEG of v4f32 to Expand. It's legal.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168030 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Make FNEG and FABS of v4f32 Expand.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168029 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Add llvm.ceil, llvm.trunc, llvm.rint, llvm.nearbyint intrinsics.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168025 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14The code pattern "imm0_255_neg" is used for checking if an immediate value ↵Nadav Rotem
is a small negative number. This patch changes the definition of negative from -0..-255 to -1..-255. I am changing this because of a bug that we had in some of the patterns that assumed that "subs" of zero does not set the carry flag. rdar://12028498 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167963 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Use __aeabi_read_tp for non-naclDavid Sehr
Fixes an introduced if statement to use the upstream version when other than nacl targets are used. BUG= http://code.google.com/p/nativeclient/issues/detail?id=1711 Review URL: https://codereview.chromium.org/11410094
2012-11-14Implement sandboxing of NEON store instructionsEli Bendersky
BUG=http://code.google.com/p/nativeclient/issues/detail?id=3124 Review URL: https://codereview.chromium.org/11361249
2012-11-13Merge commit 'be02a90de17f857ba65bbd8a11653ca1bad30adc'Derek Schuff
Conflicts: lib/Target/Mips/MipsISelLowering.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrFormats.td
2012-11-14Use TARGET2 relocation for TType references on ARM.Anton Korobeynikov
Do some cleanup of the code while here. Inspired by patch by Logan Chien! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167904 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Fix thumb2 jump relocation testDavid Sehr
Enable return address stack feature Use DwarfCFI only for NaCl BUG= http://code.google.com/p/nativeclient/issues/detail?id=3124 TEST=thumb_jump24_fixup.ll Review URL: https://codereview.chromium.org/11360241
2012-11-12misched: Target-independent support for load/store clustering.Andrew Trick
This infrastructure is generally useful for any target that wants to strongly prefer two instructions to be adjacent after scheduling. A following checkin will add target-specific hooks with unit tests. Then this feature will be enabled by default with misched. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167742 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-10Disable the Thumb no-return call optimization:Evan Cheng
mov lr, pc b.w _foo The "mov" instruction doesn't set bit zero to one, it's putting incorrect value in lr. It messes up backtraces. rdar://12663632 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167657 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09Add ARM TARGET2 relocation. The testcase will follow with actualy use-case.Anton Korobeynikov
Based on the patch by Logan Chien! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167633 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09Revert r167620; this can be implemented using an existing CL option.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167622 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09Add support for -mstrict-align compiler option for ARM targets.Chad Rosier
rdar://12340498 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167620 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-08Add @nacl.read.tp() intrinsic, a fast version of NaCl's tls_get() IRT interfaceMark Seaborn
This is in preparation for adding an LLVM pass that will expand out TLS (thread_local) variable accesses into calls to nacl.read.tp. On ARM, there is already an arm.thread.pointer intrinsic. We reuse the code for that. On x86, we have to add an implementation. The added code is based on x86's LowerToTLSExecModel() for the %gs:0 case, and on NaCl-MIPS' LowerGlobalTLSAddress() for the __nacl_read_tp() case. (In contrast, X86NaClRewritePass.cpp inserts a __nacl_read_tp() call at the lower MI level; we don't use that approach here.) We convert LowerINTRINSIC_WO_CHAIN() into a method in order to access the Subtarget member. This is consistent with other x86 Lower methods and with the ARM version. BUG=https://code.google.com/p/nativeclient/issues/detail?id=2837 TEST="llvm-lit test/NaCl" Review URL: https://codereview.chromium.org/11383002
2012-11-08Recommit modified r167540.Amara Emerson
Improve ARM build attribute emission for architectures types. This also changes the default architecture emitted for a generic CPU to "v7". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167574 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07Remove unused Td file (archaeology)Eli Bendersky
BUG=none Review URL: https://codereview.chromium.org/11368125
2012-11-07Revert r167540 until regression tests are updated.Amara Emerson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167545 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07Improve ARM build attribute emission for architectures types.Amara Emerson
This also changes the default architecture emitted for a generic CPU to "v7". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167540 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07[arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier
classes. For my test case the number of errors drop from 356 to 21. Part of rdar://12594152 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167508 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-06Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering allChad Rosier
registers. Previously, the register we being marked as implicitly defined, but not killed. In some cases this would cause the register scavenger to spill a dead register. Also, use an empty register mask to simplify the logic and to reduce the memory footprint. rdar://12592448 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167499 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-06Merge commit 'cfe09ed28d8a65b671e8b7a716a933e98e810e32'Derek Schuff
Conflicts: lib/Target/ARM/ARMFrameLowering.cpp lib/Target/Mips/MipsRegisterInfo.cpp lib/Target/X86/X86ISelLowering.cpp lib/Transforms/IPO/ExtractGV.cpp tools/Makefile tools/gold/gold-plugin.cpp The only interesting conflict was X86ISelLowering.ccp, which meant I had to essentially revert r167104. The problem is that we are using ESP as the stack pointer in X86ISelLowering and RSP as the stack pointer in X86FrameLowering, and that revision made them both consistently use X86RegisterInfo to determine which to use.
2012-11-02Vext Lowering was missing opportunitiesQuentin Colombet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167318 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-01When ARM triple CPU is unknown, assume +neon like in upstream LLVM.Eli Bendersky
This is related to issues #2751 and #3124. Neon support was added to the ARM validator recently. BUG= http://code.google.com/p/nativeclient/issues/detail?id=2751 Review URL: https://codereview.chromium.org/11368034
2012-11-01Revert the series of commits starting with r166578 which introduced theChandler Carruth
getIntPtrType support for multiple address spaces via a pointer type, and also introduced a crasher bug in the constant folder reported in PR14233. These commits also contained several problems that should really be addressed before they are re-committed. I have avoided reverting various cleanups to the DataLayout APIs that are reasonable to have moving forward in order to reduce the amount of churn, and minimize the number of commits that were reverted. I've also manually updated merge conflicts and manually arranged for the getIntPtrType function to stay in DataLayout and to be defined in a plausible way after this revert. Thanks to Duncan for working through this exact strategy with me, and Nick Lewycky for tracking down the really annoying crasher this triggered. (Test case to follow in its own commit.) After discussing with Duncan extensively, and based on a note from Micah, I'm going to continue to back out some more of the more problematic patches in this series in order to ensure we go into the LLVM 3.2 branch with a reasonable story here. I'll send a note to llvmdev explaining what's going on and why. Summary of reverted revisions: r166634: Fix a compiler warning with an unused variable. r166607: Add some cleanup to the DataLayout changes requested by Chandler. r166596: Revert "Back out r166591, not sure why this made it through since I cancelled the command. Bleh, sorry about this! r166591: Delete a directory that wasn't supposed to be checked in yet. r166578: Add in support for getIntPtrType to get the pointer type based on the address space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167221 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31llvm: build with fewer warningsJan Voung
Warnings: unused variables, unused functions, -Wreorder, and remember to return a value in a non-void function. Also remove setjmp/longjmp intrinsics for x86, which aren't being used now (no equivalents in ARM and no equivalent for x86-64 with the zero-based sandbox, etc.). This exposes a few more unused functions. BUG= none TEST= test-all Review URL: https://codereview.chromium.org/11345016
2012-10-30Align ARM stack 0mod16.David Sehr
Includes change to add some asserts to legalizing addresses for NaCl. BUG= http://code.google.com/p/nativeclient/issues/detail?id=3116 TEST=none Review URL: https://codereview.chromium.org/11285009
2012-10-30Add ARM M23 under an option.David Sehr
This will aid supporting M23 for our key applications. BUG=none TEST=none Review URL: https://codereview.chromium.org/11345042
2012-10-30Change ForceSizeOpt attribute into MinSize attributeQuentin Colombet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167020 91177308-0d34-0410-b5e6-96231b3b80d8
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