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2011-08-03New approach to r136737: insert the necessary fences for atomic ops in ↵Eli Friedman
platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing. I think this completes the basic CodeGen for atomicrmw and cmpxchg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136813 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-02ARM backend support for atomicrmw and cmpxchg with non-monotonic ordering. ↵Eli Friedman
Not especially pretty, but seems to work well enough. If this looks okay, I'll put together similar patches for Mips, PPC, and Alpha. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136737 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-02Fix the broken encodings for the VFP vmov.f32 and vmov.f64 instructions, as ↵Owen Anderson
well as the comments that explain them incorrectly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136707 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-02Tidy up. 80 columns.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136705 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-02ARM: rename addrmode7 to addr_offset_none.Jim Grosbach
Use a more descriptive name so the code is more self-documenting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136704 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-01Move imm0_255 to ARMInstrInfo.td with the other immediate predicates.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136656 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-01Fix comments.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136655 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-01Update CMake target names for tablegen-generated data in the X86 and ARM ↵Douglas Gregor
targets. This should fix the CMake build with MSVC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136621 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Add support for the 'Q' constraint.Eric Christopher
Fixes rdar://9866494 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136523 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29ARM SRS instruction parsing, diassembly and encoding support.Jim Grosbach
Fix the instruction encoding for operands. Refactor mode to use explicit instruction definitions per FIXME to be more consistent with loads/stores. Fix disassembler accordingly. Add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136509 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29ARM CPS mode immediate is 5 bits, not 4.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29ARM assembly parsing and encoding for RFE instruction.Jim Grosbach
Fill in the missing fixed bits and the register operand bits of the instruction encoding. Refactor the definition to make the mode explicit, which is consistent with how loads and stores are normally represented and makes parsing much easier. Add parsing aliases for pseudo-instruction variants. Update the disassembler for the new representations. Add tests for parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136479 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29ARM SRS and RFE instructions are not code-gen only.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136475 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29ARM range checking for mode on CPS instruction.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136473 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Update FIXME.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136470 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Tweak comment.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136468 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Transfer implicit operands in NEONMoveFixPass.Jakob Stoklund Olesen
Later passes /are/ using this information when running the register scavenger. This fixes the second problem in PR10520. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136440 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Add -verify-arm-pseudo-expand.Jakob Stoklund Olesen
This hidden llc option runs the machine code verifier after expanding ARM pseudo-instructions, but before if-conversion. The machine code verifier is much better at pointing out liveness errors that can trip up the register scavenger. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136439 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Rewrite the CMake build to use explicit dependencies between libraries,Chandler Carruth
specified in the same file that the library itself is created. This is more idiomatic for CMake builds, and also allows us to correctly specify dependencies that are missed due to bugs in the GenLibDeps perl script, or change from compiler to compiler. On Linux, this returns CMake to a place where it can relably rebuild several targets of LLVM. I have tried not to change the dependencies from the ones in the current auto-generated file. The only places I've really diverged are in places where I was seeing link failures, and added a dependency. The goal of this patch is not to start changing the dependencies, merely to move them into the correct location, and an explicit form that we can control and change when necessary. This also removes a serialization point in the build because we don't have to scan all the libraries before we begin building various tools. We no longer have a step of the build that regenerates a file inside the source tree. A few other associated cleanups fall out of this. This isn't really finished yet though. After talking to dgregor he urged switching to a single CMake macro to construct libraries with both sources and dependencies in the arguments. Migrating from the two macros to that style will be a follow-up patch. Also, llvm-config is still generated with GenLibDeps.pl, which means it still has slightly buggy dependencies. The internal CMake 'llvm-config-like' macro uses the correct explicitly specified dependencies however. A future patch will switch llvm-config generation (when using CMake) to be based on these deps as well. This may well break Windows. I'm getting a machine set up now to dig into any failures there. If anyone can chime in with problems they see or ideas of how to solve them for Windows, much appreciated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136433 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28PLD and PLI are not predicable in ARM mode.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136427 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28ARM assembly parsing and encoding for BLX (immediate).Jim Grosbach
Add parsing support for BLX (immediate). Since the register operand version is predicated and the label operand version is not, we have to use some special handling to get the operand list right for matching. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136406 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28ARM assembly parsing and encoding for BFC and BFI.Jim Grosbach
Add parsing support that handles converting the lsb+width source into the odd way we represent the instruction (an inverted bitfield mask). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136399 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28Add fixme.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136375 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28Update comments.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136367 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28Fill in some encoding information for STRD instructions.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136366 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28Revert r136295. It broke nightly testers because some parts of codegen ↵Owen Anderson
weren't aware of the changes to operand ordering. I hope to revive this sometime in the future, but it's not strictly necessary for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136362 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28ARM parsing and encoding for ADR.Jim Grosbach
The label does not have a '#' prefix. Add parsing and encoding tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136360 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28Explicitly declare a library dependency of LLVM*Desc toOscar Fuentes
LLVM*AsmPrinter. GenLibDeps.pl fails to detect vtable references. As this is the only referenced symbol from LLVM*Desc to LLVM*AsmPrinter on optimized builds, the algorithm that creates the list of libraries to be linked into tools doesn't know about the dependency and sometimes places the libraries on the wrong order, yielding error messages like this: ../../lib/libLLVMARMDesc.a(ARMMCTargetDesc.cpp.o): In function `llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo const&)': ARMMCTargetDesc.cpp:(.text._ZN4llvm14ARMInstPrinterC1ERKNS_9MCAsmInfoE [llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo const&)]+0x2a): undefined reference to `vtable for llvm::ARMInstPrinter' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136328 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27Refactor and improve the encodings/decodings for addrmode3 loads, and make ↵Owen Anderson
the writeback operand always the first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136295 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.Evan Cheng
This can happen in cases where TableGen generated asm matcher cannot check whether a register operand is in the right register class. e.g. mem operands. rdar://8204588 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136292 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27ARM assembly parsing and encoding support for USAT and USAT16.Jim Grosbach
Use range checked immediate operands for instructions. Add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136285 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27Code generation for 'fence' instruction.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27ARM assembly parsing and encoding for UMULL.Jim Grosbach
Fix parsing of the 's' suffix for the mnemonic. Add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136277 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27ARM assembly parsing and encoding for UMLAL.Jim Grosbach
Fix parsing of the 's' suffix for the mnemonic. Add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136274 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27ARM parsing and encoding of SBFX and UBFX.Jim Grosbach
Encode the width operand as it encodes in the instruction, which simplifies the disassembler and the encoder, by using the imm1_32 operand def. Add a diagnostic for the context-sensitive constraint that the width must be in the range [1,32-lsb]. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27Refactor the STRT and STRBT instructions to distinguish between the ↵Owen Anderson
register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136255 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27ARM assembly parsing and encoding for extend instructions.Jim Grosbach
Assembly parser handling for extend instruction rotate operands. Add tests for the sign extend instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136252 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27ARM assembly parsing aliases for extend instructions w/o rotate.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136229 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27ARM cleanup of remaining extend instructions.Jim Grosbach
Refactor the rest of the extend instructions to not artificially distinguish between a rotate of zero and a rotate of any other value. Replace the by-zero versions with Pat<>'s for ISel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136226 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27ARM extend instructions simplification.Jim Grosbach
Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136225 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27Support .code32 and .code64 in X86 assembler.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136197 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26ARM rot_imm printing adjustment.Jim Grosbach
Allow the rot_imm operand to be optional. This sets the stage for refactoring away the "rr" versions from the multiclasses and replacing them with Pat<>s. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136154 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26ARM cleanup of rot_imm encoding.Jim Grosbach
Start of cleaning this up a bit. First step is to remove the encoder hook by storing the operand as the bits it'll actually encode to so it can just be directly used. Map it to the assembly source values 8/16/24 when we print it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26Split am2offset into register addend and immediate addend forms, necessary ↵Owen Anderson
for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26Fix over-zealous rename from r136095.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136132 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26ARM diagnostics for ldrexd/stredx out of order paired register operands.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136110 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26ARM fix for LDREX source register encoding.Jim Grosbach
rdar://9842203 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26ARM assembly parsing and encoding for SWP[B] instructions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26ARM SWP instructions store, too, not just load.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26Clean up the ARM asm parser a bit.Jim Grosbach
No intendeded functional change. Just cleaning up a bit to make things more self-consistent in layout and style. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136095 91177308-0d34-0410-b5e6-96231b3b80d8
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