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2012-08-24Explicitly mark LEApcrel pseudos with hasSideEffects.Jakob Stoklund Olesen
It's not clear that they should be marked as such, but tbb formation fails if t2LEApcrelJT is hoisted of of a loop. This doesn't change the flags on these instructions, UnmodeledSideEffects was already inferred from the missing pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162603 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Remove llvm.nacl.tp.alignment intrinsicDerek Schuff
This intrinsic is no longer used by untrusted code's libpthread. Instead the system (the IRT and/or TCB) is responsible for aligning the stack in new threads. R= jvoung@chromium.org,sehr@chromium.org BUG= http://code.google.com/p/nativeclient/issues/detail?id=2924 TEST=run_stack_alignment_test Review URL: https://chromiumcodereview.appspot.com/10871069
2012-08-24Fix call instruction operands in ARMFastISel.Jakob Stoklund Olesen
The ARM BL and BLX instructions don't have predicate operands, but the thumb variants tBL and tBLX do. The argument registers should be added as implicit uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162593 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Add missing SDNPSideEffect flags.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162557 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Fix undefined behavior (negation of INT_MIN) in ARM backend.Richard Smith
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162520 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23Remove the llvm.nacl.thread.stack.padding intrinsicMark Seaborn
This intrinsic is no longer used by untrusted code's libpthread. Instead the system (the IRT and/or TCB) is responsible for aligning the stack in new threads. BUG=http://code.google.com/p/nativeclient/issues/detail?id=2904 TEST=run_stack_alignment_test Review URL: https://chromiumcodereview.appspot.com/10874034
2012-08-22Reduce duplicated hash map lookups.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162362 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper
did getFunction()->getName(). Remove includes of Function.h that are no longer needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162347 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-21Merge up to r162331, git commit bc363931085587bac42a40653962a3e5acd1ffceDerek Schuff
2012-08-21Add a missing def flag.Jakob Stoklund Olesen
*** Bad machine code: Explicit definition marked as use *** - function: test_cos - basic block: BB#0 L.entry (0x7ff2a2024fd0) - instruction: VSETLNi32 %D11, %D11<undef>, %R0, 0, pred:14, pred:%noreg, %Q5<imp-use,kill>, %Q5<imp-def> - operand 0: %D11 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162247 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-20Use a SmallPtrSet to dedup successors in EmitSjLjDispatchBlock.Jakob Stoklund Olesen
The test case ARM/2011-05-04-MultipleLandingPadSuccs.ll was creating duplicate successor list entries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162222 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-18Remove the CAND/COR/CXOR custom ISD nodes and their select code.Jakob Stoklund Olesen
These nodes are no longer needed because the peephole pass can fold CMOV+AND into ANDCC etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162179 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-18Remove virtual from many methods. These methods replace methods in the base ↵Craig Topper
class, but the base class methods aren't virtual so it just increased call overhead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162178 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-18Also combine zext/sext into selects for ARM.Jakob Stoklund Olesen
This turns common i1 patterns into predicated instructions: (add (zext cc), x) -> (select cc (add x, 1), x) (add (sext cc), x) -> (select cc (add x, -1), x) For a function like: unsigned f(unsigned s, int x) { return s + (x>0); } We now produce: cmp r1, #0 it gt addgt.w r0, r0, #1 Instead of: movs r2, #0 cmp r1, #0 it gt movgt r2, #1 add r0, r2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162177 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-18Also pass logical ops to combineSelectAndUse.Jakob Stoklund Olesen
Add these transformations to the existing add/sub ones: (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) (or (select cc, 0, c), x) -> (select cc, x, (or, x, c)) (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c)) The selects can then be transformed to a single predicated instruction by peephole. This transformation will make it possible to eliminate the ISD::CAND, COR, and CXOR custom DAG nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162176 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-18fp16-to-fp32 conversion instructions are available in Thumb mode as well.Anton Korobeynikov
Make sure the generic pattern is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162170 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17Merge commit 'c723eb1aef817d47feec620933ee1ec6005cdd14'Derek Schuff
This merges r159618 from upstream into master. It goes with clang rev af50aab0c317462129d73ae8000c6394c718598d Conflicts: include/llvm/CodeGen/LexicalScopes.h include/llvm/Target/TargetOptions.h lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMTargetMachine.cpp lib/Target/ARM/ARMTargetObjectFile.cpp lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp lib/Target/Mips/MipsISelDAGToDAG.cpp lib/Target/Mips/MipsInstrFPU.td lib/Target/Mips/MipsMCInstLower.cpp lib/Target/Mips/MipsTargetMachine.cpp lib/Target/TargetMachine.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86RegisterInfo.cpp lib/Target/X86/X86TargetObjectFile.cpp lib/Target/X86/X86TargetObjectFile.h tools/llc/llc.cpp (tools/llc/llc.cpp is from a merged version of r160532 because it was a bit hairy and I didn't want to redo it.)
2012-08-17Avoid folding ADD instructions with FI operands.Jakob Stoklund Olesen
PEI can't handle the pseudo-instructions. This can be removed when the pseudo-instructions are replaced by normal predicated instructions. Fixes PR13628. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162130 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17Add comment, clean up code. No functional change.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162107 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17Implement NEON domain switching for scalar <-> S-register vmovs on ARMTim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162094 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17Remove unnecessary include of ARMGenInstrInfo.inc.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-16Add ADD and SUB to the predicable ARM instructions.Jakob Stoklund Olesen
It is not my plan to duplicate the entire ARM instruction set with predicated versions. We need a way of representing predicated instructions in SSA form without requiring a separate opcode. Then the pseudo-instructions can go away. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162061 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-16Handle ARM MOVCC optimization in PeepholeOptimizer.Jakob Stoklund Olesen
Use the target independent select analysis hooks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162060 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-16[arm-fast-isel] Add support for fastcc.Jush Lu
Without fastcc support, the caller just falls through to CallingConv::C for fastcc, but callee still uses fastcc, this inconsistency of calling convention is a problem, and fastcc support can fix it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162013 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-15Fold predicable instructions into MOVCC / t2MOVCC.Jakob Stoklund Olesen
The ARM select instructions are just predicated moves. If the select is the only use of an operand, the instruction defining the operand can be predicated instead, saving one instruction and decreasing register pressure. This implementation can turn AND/ORR/EOR instructions into their corresponding ANDCC/ORRCC/EORCC variants. Ideally, we should be able to predicate any instruction, but we don't yet support predicated instructions in SSA form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161994 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-15Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows ↵Evan Cheng
unaligned access. rdar://12091029 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161962 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-15Add missing Rfalse operand to the predicated pseudo-instructions.Jakob Stoklund Olesen
When predicating this instruction: Rd = ADD Rn, Rm We need an extra operand to represent the value given to Rd when the predicate is false: Rd = ADDCC Rfalse, Rn, Rm, pred The Rd and Rfalse operands are different registers while in SSA form. Rfalse is tied to Rd to make sure they get the same register during register allocation. Previously, Rd and Rn were tied, but that is not required. Compare to MOVCC: Rd = MOVCC Rfalse, Rtrue, pred git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161955 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14The names of VFP variants of half-to-float conversion instructions wereAnton Korobeynikov
reversed. This leads to wrong codegen for float-to-half conversion intrinsics which are used to support storage-only fp16 type. NEON variants of same instructions are fine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161907 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14This needs braces. Spotted by Bill.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161906 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14Switch the fixed-length disassembler to be table-driven.Jim Grosbach
Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161888 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13Remove the TII::scheduleTwoAddrSource() hook.Jakob Stoklund Olesen
It never does anything when running 'make check', and it get's in the way of updating live intervals in 2-addr. The hook was originally added to help form IT blocks in Thumb2 code before register allocation, but the pass ordering has changed since then, and we run if-conversion after register allocation now. When the MI scheduler is enabled, there will be no less than two schedulers between 2-addr and Thumb2ITBlockPass, so this hook is unlikely to help anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161794 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13ARM: enable struct byval for AAPCS-VFP.Manman Ren
This change is to be enabled in clang. rdar://9877866 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161789 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13Do not optimize (or (and X,Y), Z) into BFI and other sequences if the AND ↵Nadav Rotem
ISDNode has more than one user. rdar://11876519 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161775 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13Add support for the %H output modifier.Eric Christopher
Patch by Weiming Zhao. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161768 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13Use correct loads for vector types during extending-load operations.Tim Northover
Previously, we used VLD1.32 in all cases, however there are both 16 and 64-bit accesses being selected, so we need to use an appropriate width load in those cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161748 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-12Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARMArnold Schwaighofer
architecture It broke MultiSource/Applications/JM/ldecod/ldecod on armv7 thumb O0 g and armv7 thumb O3. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161736 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-12Change addTypeForNeon to use MVT instead of EVT so all the calls to ↵Craig Topper
getSimpleVT can be removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161735 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10ARM: enable struct byval for AAPCS.Manman Ren
This change is to be enabled in clang. rdar://9877866 PR://13350 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161693 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09Remove getARMRegisterNumbering and replace with calls intoEric Christopher
the register info for getEncodingValue. This builds on the small patch of yesterday to set HWEncoding in the register file. One (deprecated) use was turned into a hard number to avoid needing register info in the old JIT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161628 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09Patch to implement UMLAL/SMLAL instructions for the ARM architectureArnold Schwaighofer
This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161581 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09This field isn't used anymore, use it with HWEncoding instead.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161564 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08Added MispredictPenalty to SchedMachineModel.Andrew Trick
This replaces an existing subtarget hook on ARM and allows standard CodeGen passes to potentially use the property. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161471 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161469 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-04Skip impdef regs during eabi save/restore list emission to workaround PR11902Anton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161301 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-04Recognize vst1.64 / vld1.64 with 3 and 4 regs as load from / store to stack ↵Anton Korobeynikov
stuff (this corresponds by spilling/reloading regs in DTriple / DQuad reg classes). No testcase, found by inspection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161300 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-04Add stack spill / reload instructions for DTriple and DQuad register ↵Anton Korobeynikov
classes, which were missed for no reason. This fixes PR13377 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161299 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03Fall back to selection DAG isel for calls to builtin functions.Bob Wilson
Fast isel doesn't currently have support for translating builtin function calls to target instructions. For embedded environments where the library functions are not available, this is a matter of correctness and not just optimization. Most of this patch is just arranging to make the TargetLibraryInfo available in fast isel. <rdar://problem/12008746> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161232 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03[arm-fast-isel] Add support for shl, lshr, and ashr.Jush Lu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161230 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03Add support for the ARM GHC calling convention, this patch was in 3.0,Eric Christopher
but somehow managed to be dropped later. Patch by Karel Gardas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02ARM: Tidy up. Remove unused template parameters.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161222 91177308-0d34-0410-b5e6-96231b3b80d8
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