| Age | Commit message (Expand) | Author |
|---|
| 2012-03-05 | ARM Refactor VLD/VST spaced pair instructions. | Jim Grosbach |
| 2012-03-05 | ARM refactor away a bunch of VLD/VST pseudo instructions. | Jim Grosbach |
| 2012-02-29 | Make MemoryObject accessor members const again | Derek Schuff |
| 2012-02-27 | Fix the symbolic operand added for the C disassmbler API for the ARM bl | Kevin Enderby |
| 2012-02-23 | Updated the llvm-mc disassembler C API to support for the X86 target. | Kevin Enderby |
| 2012-02-18 | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu |
| 2012-02-11 | Make the EDis tables const. | Benjamin Kramer |
| 2012-02-07 | Convert assert(0) to llvm_unreachable | Craig Topper |
| 2012-02-06 | Enable streaming of bitcode | Derek Schuff |
| 2012-01-20 | More dead code removal (using -Wunreachable-code) | David Blaikie |
| 2011-12-15 | ARM NEON VTBL/VTBX assembly parsing and encoding. | Jim Grosbach |
| 2011-12-14 | ARM NEON refactor VST2 w/ writeback instructions. | Jim Grosbach |
| 2011-12-14 | ARM NEON VST2 assembly parsing and encoding. | Jim Grosbach |
| 2011-12-09 | ARM assembly parsing and encoding for VLD2 with writeback. | Jim Grosbach |
| 2011-11-30 | Remove unused variable | Matt Beaumont-Gay |
| 2011-11-30 | ARM parsing for VLD1 all lanes, with writeback. | Jim Grosbach |
| 2011-11-29 | ARM assembly parsing and encoding for four-register VST1. | Jim Grosbach |
| 2011-11-29 | ARM assembly parsing and encoding for three-register VST1. | Jim Grosbach |
| 2011-11-15 | Fix a misplaced paren bug. | Owen Anderson |
| 2011-11-15 | Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VM... | Owen Anderson |
| 2011-11-12 | Re-apply 144430, this time with the associated isel and disassmbler bits. | Jim Grosbach |
| 2011-11-11 | Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler. | Benjamin Kramer |
| 2011-11-02 | The rules disallowing single-register reglist operands only apply to the POP ... | Owen Anderson |
| 2011-11-02 | Register list operands are not allowed to contain only a single register. Al... | Owen Anderson |
| 2011-11-01 | Fix disassembly of some VST1 instructions. | Owen Anderson |
| 2011-10-31 | ARM VST1 w/ writeback assembly parsing and encoding. | Jim Grosbach |
| 2011-10-31 | More not-crashing NEON disassembly updates for the vld refactoring. | Owen Anderson |
| 2011-10-28 | Reapply r143202, with a manual decoding hook for SWP. This change inadvertan... | Owen Anderson |
| 2011-10-27 | Add some NEON stores to the VLD decoding hook that were accidentally omitted ... | Owen Anderson |
| 2011-10-25 | ARM assembly parsing and encoding for VLD1 with writeback. | Jim Grosbach |
| 2011-10-24 | ARM assembly parsing and encoding for VLD1 w/ writeback. | Jim Grosbach |
| 2011-10-24 | ARM refactor am6offset usage for VLD1. | Jim Grosbach |
| 2011-10-24 | Fix a NEON disassembly case that was broken in the recent refactorings. As m... | Owen Anderson |
| 2011-10-22 | Move various generated tables into read-only memory, fixing up const correctn... | Benjamin Kramer |
| 2011-10-21 | Assembly parsing for 4-register sequential variant of VLD2. | Jim Grosbach |
| 2011-10-21 | Assembly parsing for 2-register sequential variant of VLD2. | Jim Grosbach |
| 2011-10-21 | Assembly parsing for 4-register variant of VLD1. | Jim Grosbach |
| 2011-10-21 | Assembly parsing for 3-register variant of VLD1. | Jim Grosbach |
| 2011-10-21 | ARM VLD parsing and encoding. | Jim Grosbach |
| 2011-10-20 | Tidy up. Trailing whitespace. | Jim Grosbach |
| 2011-10-17 | Removed set, but unused variables. | Chad Rosier |
| 2011-10-14 | Fix a non-firing assert. Change: | Richard Trieu |
| 2011-10-13 | Fix undefined shift. Patch by Ahmed Charles. | Eli Friedman |
| 2011-10-13 | SETEND is not allowed in an IT block. | Owen Anderson |
| 2011-10-12 | ARM addrmode5 represents the 'U' bit of the encoding backwards. | Jim Grosbach |
| 2011-10-12 | Thumb2 assembly parsing and encoding for LDC/STC. | Jim Grosbach |
| 2011-10-12 | addrmode2 is gone from these, so no need for the reg0 operand. | Jim Grosbach |
| 2011-10-06 | Fix the check for nested IT instructions in the disassembler. We need to per... | Owen Anderson |
| 2011-10-04 | Adding back support for printing operands symbolically to ARM's new disassembler | Kevin Enderby |
| 2011-09-30 | ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. | Jim Grosbach |
