| Age | Commit message (Expand) | Author |
|---|
| 2011-09-26 | ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. | Owen Anderson |
| 2011-09-23 | Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid t... | Owen Anderson |
| 2011-09-23 | Revert r140412. This affects more instructions than intended. | Owen Anderson |
| 2011-09-23 | Thumb2 register-shifted-register loads cannot target the PC or the SP. | Owen Anderson |
| 2011-09-19 | tMOVSr is not allowed in an IT block either. | Owen Anderson |
| 2011-09-19 | CPS instructions are UNPREDICTABLE inside IT blocks. | Owen Anderson |
| 2011-09-19 | Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not... | Owen Anderson |
| 2011-09-19 | Thumb2 assembly parsing and encoding for TBB/TBH. | Jim Grosbach |
| 2011-09-19 | Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Por... | Owen Anderson |
| 2011-09-16 | Bitfield mask instructions are unpredictable if the encoded LSB is higher tha... | Owen Anderson |
| 2011-09-16 | Fix bitfield decoding based on Eli's feedback. | Owen Anderson |
| 2011-09-16 | Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt. | Owen Anderson |
| 2011-09-16 | Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32). | Owen Anderson |
| 2011-09-16 | Fix disassembly of Thumb2 LDRSH with a #-0 offset. | Owen Anderson |
| 2011-09-15 | Don't attach annotations to MCInst's. Instead, have the disassembler return,... | Owen Anderson |
| 2011-09-14 | Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them. | Owen Anderson |
| 2011-09-12 | Port more encoding tests to decoding tests, and correct an improper Thumb2 pr... | Owen Anderson |
| 2011-09-09 | LDM writeback is not allowed if Rn is in the target register list. | Owen Anderson |
| 2011-09-09 | Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. | Owen Anderson |
| 2011-09-09 | Thumb unconditional branches are allowed in IT blocks, and therefore should h... | Owen Anderson |
| 2011-09-09 | Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. | Jim Grosbach |
| 2011-09-08 | All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ. | Owen Anderson |
| 2011-09-08 | Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block. | Owen Anderson |
| 2011-09-08 | Thumb2 assembly parsing and encoding for LDRD(immediate). | Jim Grosbach |
| 2011-09-08 | Remove the "common" set of instructions shared between ARM and Thumb2 modes. ... | Owen Anderson |
| 2011-09-07 | Create Thumb2 versions of STC/LDC, and reenable the relevant tests. | Owen Anderson |
| 2011-09-07 | Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds p... | James Molloy |
| 2011-09-07 | Port more assembler tests over to disassembler tests, and fix a minor logic e... | Owen Anderson |
| 2011-09-07 | Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= ... | James Molloy |
| 2011-09-01 | Merge the ARM disassembler header into the implementation file, since it is n... | Owen Anderson |
| 2011-09-01 | Fix 80 columns violations. | Owen Anderson |
| 2011-09-01 | Fix up r137380 based on post-commit review by Jim Grosbach. | James Molloy |
| 2011-08-31 | The asm parser currently selects the wrong encoding for non-conditional Thumb... | Owen Anderson |
| 2011-08-30 | Fix issues with disassembly of IT instructions involving condition codes othe... | Owen Anderson |
| 2011-08-26 | Improve encoding support for BLX with immediat eoperands, and fix a BLX decod... | Owen Anderson |
| 2011-08-26 | Spelling fail. | Owen Anderson |
| 2011-08-26 | invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We w... | Owen Anderson |
| 2011-08-26 | Update for feedback from Jim. | Owen Anderson |
| 2011-08-26 | ARMDisassembler: Always return a size, even when disassembling fails. | Benjamin Kramer |
| 2011-08-26 | Support an extension of ARM asm syntax to allow immediate operands to ADR ins... | Owen Anderson |
| 2011-08-26 | Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT i... | Owen Anderson |
| 2011-08-25 | Port over additional encoding tests to decoding tests, and fix an operand ord... | Owen Anderson |
| 2011-08-24 | Perform more thorough checking of t2IT mask parameters, which fixes all remai... | Owen Anderson |
| 2011-08-24 | Be careful not to walk off the end of the operand info list while updating VF... | Owen Anderson |
| 2011-08-24 | Move TargetRegistry and TargetSelect from Target to Support where they belong. | Evan Cheng |
| 2011-08-24 | Be stricter in enforcing IT instruction predicate values, so that we don't en... | Owen Anderson |
| 2011-08-23 | Fix decoding of Thumb2 prefetch instructions, which account for all the remai... | Owen Anderson |
| 2011-08-23 | Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same in... | Owen Anderson |
| 2011-08-22 | Reject invalid imod values in t2CPS instructions. | Owen Anderson |
| 2011-08-22 | Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming major... | Owen Anderson |
