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path: root/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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2011-11-01ARM label operands can have an optional '#' before them.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143510 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-01ARM VLD/VST assembly parsing for symbolic address operands.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143413 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-31ARM VST1 w/ writeback assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143369 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-28ARM mode 'mov' to 'mvn' assembler alias.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143237 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-28Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".Jim Grosbach
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example, mov r2, #-3 becomes mvn r2, #2 rdar://10349224 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143235 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-28ARM Allow 'q' registers in VLD/VST vector lists.Jim Grosbach
Just treat it as if the constituent D registers where specified. rdar://10348896 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143167 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26Thumb2 ldr pc-relative encoding fixes.Jim Grosbach
We were parsing label references to the i12 encoding, which isn't right. They need to go to the pci variant instead. More of rdar://10348687 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143068 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26ARM parse parenthesized expressions for label references.Jim Grosbach
Partial fix for rdar://10348687. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach
One and two length register list variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142861 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-22Move various generated tables into read-only memory, fixing up const ↵Benjamin Kramer
correctness along the way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142726 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21Assembly parsing for 2-register sequential variant of VLD2.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21Assembly parsing for 4-register variant of VLD1.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21Assembly parsing for 3-register variant of VLD1.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21ARM VLD parsing and encoding.Jim Grosbach
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle VLD1 instructions that take a two-register register list. Adjust the instruction definitions to only have the single encoded register as an operand. The super-register from the pseudo is kept as an implicit def, so passes which come after pseudo-expansion still know that the instruction defines the other subregs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21Don't automatically set the "fc" bits on MSR instructions if the user didn't ↵Owen Anderson
ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142669 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21Nuke an #if0 that got accidentally left in.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142658 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18ARM VTBL (one register) assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142441 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18ARM assembly parsing and encoding for VMOV.i64.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142321 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142303 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Tidy up.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142297 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17ARM NEON "vmov.i8" immediate assembly parsing and encoding.Jim Grosbach
NEON immediates are "interesting". Start of the work to handle parsing them in an 'as' compatible manner. Getting the matcher to play nicely with these and the floating point immediates from VFP is an extra fun wrinkle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Removed set, but unused variables.Chad Rosier
Patch by Joe Abbey <jabbey@arxan.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142223 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Thumb2 assembly parsing and encoding for LDC/STC.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12ARM parsing and encoding for the <option> form of LDC/STC instructions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.Jim Grosbach
Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141721 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11ARM parse alignment specifier for NEON load/store instructions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11ARM Rename operand sub-structure 'Mem' to 'Memory' for a bit more clarity.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141671 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Simplify operand Kind checks a bit.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07ARM NEON assembly parsing and encoding for VDUP(scalar).Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07ARM prefix asmparser operand kind enums for readability.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141438 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07Improve ARM assembly parser diagnostic for unexpected tokens.Jim Grosbach
Consider: mov r8, r11 fred Previously, we issued the not very informative: x.s:6:1: error: unexpected token in argument list ^ Now we generate: x.s:5:14: error: unexpected token in argument list mov r8, r11 fred ^ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141380 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Support a valid, but not very useful, encoding of CPSIE where none of the ↵Owen Anderson
AIF bits are set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141190 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03ARM assembly parsing and encoding for VMOV immediate.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03ARM parsing/encoding for VCMP/VCMPE.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03ARM assembly parsing and encoding for VMRS/FMSTAT.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28Check in a patch that has already been code reviewed by Owen that I'd ↵James Molloy
forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset ↵Owen Anderson
of #-0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140426 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140095 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19Thumb2 assembly parsing and encoding for TBB/TBH.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19ARM asm parsing should handle pre-indexed writeback w/o immediate.Jim Grosbach
For example, 'ldrb r9, [sp]!' is odd, but valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140035 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16Thumb2 assembly parsing and encoding for SUB(immediate).Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139966 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16Thumb2 assembly parsing and encoding for STR.Jim Grosbach
More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH and STR(register). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16Thumb2 assembly parsing and encoding for STMIA.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139938 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16Thumb2 assembly parsing and encoding for SMMULL.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16Kill some dead code.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139904 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16Tidy up a bit.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139903 91177308-0d34-0410-b5e6-96231b3b80d8
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