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path: root/lib/Target/ARM/ARMISelLowering.cpp
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2011-07-27Code generation for 'fence' instruction.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27ARM extend instructions simplification.Jim Grosbach
Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136225 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, ↵Owen Anderson
allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135693 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng
ARM MC code from target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18land David Blaikie's patch to de-constify Type, with a few tweaks.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135375 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13Improve codegen for select's:Evan Cheng
if (x != 0) x = 1 if (x == 1) x = 1 Previous codegen looks like this: mov r1, r0 cmp r1, #1 mov r0, #0 moveq r0, #1 The naive lowering select between two different values. It should recognize the test is equality test so it's more a conditional move rather than a select: cmp r0, #1 movne r0, #0 rdar://9758317 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08Add an intrinsic and codegen support for fused multiply-accumulate. The intentCameron Zwarich
is to use this for architectures that have a native FMA instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134742 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08Add more info to FIXME.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134729 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01ARMv7M vs. ARMv7E-M support.Jim Grosbach
The DSP instructions in the Thumb2 instruction set are an optional extension in the Cortex-M* archtitecture. When present, the implementation is considered an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation." Add a subtarget feature hook for the v7e-m instructions and hook it up. The cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is a v7e-m implementation. rdar://9572992 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134261 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01Add support for the 'j' immediate constraint. This is conditionalized onEric Christopher
supporting the instruction that the constraint is for 'movw'. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134222 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01Add support for the ARM 't' register constraint. And another testcaseEric Christopher
for the 'x' register constraint. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134220 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01We'll return a null RC by default if we can't match.Eric Christopher
Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134217 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01Add support for the 'x' constraint.Eric Christopher
Part of rdar://9307836 and rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134215 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30Capitalize the unsigned part of the initializer.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134211 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30Rename Pair to RCPair lacking any better naming ideas.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134210 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30Add support for the 'h' constraint.Eric Christopher
Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134203 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30Add a convenience typedef for std::pair<unsigned, const TargetRegisterClass*>.Eric Christopher
No functional change. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134198 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29Remove getRegClassForInlineAsmConstraint from the ARM port.Eric Christopher
Part of rdar://9643582 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134095 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng
sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28Remove warning: 'c0' may be used uninitialized in this function.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134014 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24The Neon VCVT (between floating-point and fixed-point, Advanced SIMD) Chad Rosier
instructions can be used to match combinations of multiply/divide and VCVT (between floating-point and integer, Advanced SIMD). Basically the VCVT immediate operand that specifies the number of fraction bits corresponds to a floating-point multiply or divide by the corresponding power of 2. For example, VCVT (floating-point to fixed-point, Advanced SIMD) can replace a combination of VMUL and VCVT (floating-point to integer) as follows: Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vmul.f32 d16, d17, d16 vcvt.s32.f32 d16, d16 becomes: vcvt.s32.f32 d16, d16, #3 Similarly, VCVT (fixed-point to floating-point, Advanced SIMD) can replace a combinations of VCVT (integer to floating-point) and VDIV as follows: Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vcvt.f32.s32 d16, d16 vdiv.f32 d16, d17, d16 becomes: vcvt.f32.s32 d16, d16, #3 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133813 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21Handle the memory-ness of all U+ ARM constraints.Eric Christopher
Noticed on inspection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133553 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18Remove unused but set variables.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133347 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16Mark ldrexd/strexd w/ volatile memory by defaultBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133175 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16Revision r128665 added an optimization to make use of NEON multiplierChad Rosier
accumulator forwarding. Specifically (from SVN log entry): Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier accumulator forwarding: vadd d3, d0, d1 vmul d3, d3, d2 => vmul d3, d0, d2 vmla d3, d1, d2 Make sure it catches cases where operand 1 is add/fadd/sub/fsub, which was intended in the original revision. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133127 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15A minor simplification: no functional change.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iffEvan Cheng
the bits being cleared by the AND are not demanded by the BFI. The previous BFI dag combine rule was actually incorrect (or used to be correct until BFI representation changed). rdar://9609030 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133034 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14Add an optimization that looks for a specific pair-wise add pattern and ↵Tanya Lattner
generates a vpaddl instruction instead of scalarizing the add. Includes a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14Add one more argument to the prefetch intrinsic to indicate whether it's a dataBruno Cardoso Lopes
or instruction cache access. Update the targets to match it and also teach autoupgrade. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132976 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-10Provide an ARMCCState subclass of CCState so that ARM clients will always setCameron Zwarich
CallOrPrologue correctly and eliminate the existing setter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132856 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09A CCState was being created without setting whether it is in the Call or ↵Cameron Zwarich
Prologue state, causing an assertion failure downstream. This fixes <rdar://problem/9562908>. This really seems like it should always be set at CCState creation time, so mistakes like this can never happen. I'll take a look at doing that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-08Add a parameter to CCState so that it can access the MachineFunction.Eric Christopher
No functional change. Part of PR6965 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03Make the Uv constraint a memory operand. This doesn't solve theEric Christopher
addressing mode problem mentioned in r132559. Backend part of rdar://9037836 and part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132561 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Have LowerOperandForConstraint handle multiple character constraints.Eric Christopher
Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132510 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.John McCall
This is important for the correct lowering of unwind instructions (which doesn't matter at all) and llvm.eh.resume calls (which does). Take 2, now with more basic competence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132295 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29I didn't mean to commit these residues of a personal project.John McCall
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.John McCall
This is important for the correct lowering of unwind instructions (which doesn't matter at all) and llvm.eh.resume calls (which does). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132291 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairsBruno Cardoso Lopes
to load/store i64 values. Since there's no current support to explicitly declare such restrictions, implement it by using specific hardcoded register pairs during isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132248 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27Fix the remaining atomic intrinsics to use the right register classes on Thumb2,Cameron Zwarich
and add some basic tests for them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132235 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27Don't use movw / movt for iOS static codegen for now to workaround some ↵Evan Cheng
tools issues. rdar://9514789 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132211 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-22RTABI chapter 4.3.4 specifies __eabi_mem* calls. Specifically, __eabi_memset ↵Renato Golin
accepts parameters (ptr, size, value) in a different order than GNU's memset (ptr, value, size), therefore the special lowering in AAPCS mode. Implementation by Evzen Muller. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131868 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20Revert accidental commit.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131739 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20Revert r131664 and fix it in instcombine instead. rdar://9467055Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131708 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19Fixed sdiv and udiv for <4 x i16>. The test from r125402 still applies for ↵Mon P Wang
this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131630 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18Handle perfect shuffle case that generates a vrev for vectors of floats.Tanya Lattner
Add test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131582 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18Revise r131553. Just use the type of the input node and forgo the bitcast. ↵Evan Cheng
rdar://9449159. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131555 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same ↵Evan Cheng
type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131553 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18In r131488 I misunderstood how VREV works. It splits the vector in half and ↵Tanya Lattner
splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. Updated test case and reverted change to the PerfectShuffle Table. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131529 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18Fix typo.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131519 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18Fix more of PR8825 by correctly using rGPR registers when lowering atomicCameron Zwarich
compare-and-swap intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131518 91177308-0d34-0410-b5e6-96231b3b80d8
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