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path: root/lib/Target/ARM/ARMISelLowering.cpp
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2011-10-07Take all of the invoke basic blocks and make the dispatch basic block their newBill Wendling
successor. Remove the old landing pad from their successor list, because it's now the successor of the dispatch block. Now that the landing pad blocks are no longer the destination of invokes, we can mark them as normal basic blocks instead of landing pads. This more closely resembles what the CFG is actually doing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141436 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07Take the code that was emitted for the llvm.eh.dispatch.setup intrinsic and emitBill Wendling
it with the new SjLj emitter stuff. This way there's no need to emit that kind-of-hacky intrinsic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141419 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented toBill Wendling
do. This will be useful later on with the new SJLJ stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141416 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07Reenable tail calls for iOS 5.0 and later.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07Reenable use of divmod compiler_rt functions for iOS 5.0 and later.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141368 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07Peephole optimization for ABS on ARM.Anton Korobeynikov
Patch by Ana Pazos! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141365 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06Use the correct vreg here.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141342 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06Generate the dispatch code for a 'thumb' function. This is very similar to theBill Wendling
others. They take the call site value. Determine if it's a proper value. And then jumps to the correct call site via a jump table. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141341 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06Generate the dispatch table for ARM mode.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141327 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06Refactor some of the code that sets up the entry block for SjLj EH. No ↵Bill Wendling
functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141323 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06Use a thumb ORR instead of thumb2 ORR when in thumb-only mode. (Picky! Picky!)Bill Wendling
Place the immediate to OR into a register so that it works. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141319 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06* Set the low bit of the return address when we are in thumb mode.Bill Wendling
* Some code cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141317 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06Add the MBBs before inserting the instructions. Doing it afterwards could leadBill Wendling
to an infinite loop because of the def-use chains. Also use a frame load instead of store for the LD instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141263 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Get the proper call site numbers for the landing pads. Also remove a magicBill Wendling
number (18) for the proper addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Look at the number of entries in the jump table and jump to a 'trap' block ifBill Wendling
the value exceeds that number. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141143 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Checkpoint for SJLJ EH code.Bill Wendling
This is a first pass at generating the jump table for the sjlj dispatch. It currently generates something plausible, but hasn't been tested thoroughly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141140 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03Use the PC label ID rather than '1'. Add support for thumb-2, because I ↵Bill Wendling
heard that some people use it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141042 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03Check-pointing the new SjLj EH lowering.Bill Wendling
This code will replace the version in ARMAsmPrinter.cpp. It creates a new machine basic block, which is the dispatch for the return from a longjmp call. It then shoves the address of that machine basic block into the correct place in the function context so that the EH runtime will jump to it directly instead of having to go through a compare-and-jump-to-the-dispatch bit. This should be more efficient in the common case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141031 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01Use the new ARMConstantPoolSymbol class to handle external symbols.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140939 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01Switch over to using ARMConstantPoolConstant for global variables, functions,Bill Wendling
and block addresses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.Jim Grosbach
Encode the immediate into its 8-bit form as part of isel rather than later, which simplifies things for mapping the encoding bits, allows the removal of the custom disassembler decoding hook, makes the operand printer trivial, and prepares things more cleanly for handling these in the asm parser. rdar://10211428 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140834 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28Tighten a ARM dag combine condition to avoid an identity transformation, whichEvan Cheng
ends up introducing a cycle in the DAG. rdar://10196296 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140733 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL ↵David Meyer
2011-06-09-TailCallByVal and 2010-11-04-BigByval git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140516 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21Lower ARM adds/subs to add/sub after adding optional CPSR operand.Andrew Trick
This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140228 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20ARM isel bug fix for adds/subs operands.Andrew Trick
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the full gamut of CPSR defs/uses including instructins whose "optional" cc_out operand is not really optional. This allowed removal of the hasPostISelHook to simplify the .td files and make the implementation more robust. Fixes rdar://10137436: sqlite3 miscompile git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140133 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16Thumb2 assembly parsing and encoding for STR.Jim Grosbach
More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH and STR(register). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15Minor cleanup.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139869 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15Use a more efficient lowering for Unordered/Monotonic atomic load/store on ↵Eli Friedman
Thumb1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139865 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13Tidy up a few 80 column violations.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Thumb unconditional branches are allowed in IT blocks, and therefore should ↵Owen Anderson
have a predicate operand, unlike conditional branches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06Add codegen support for vector select (in the IR this means a selectDuncan Sands
with a vector condition); such selects become VSELECT codegen nodes. This patch also removes VSETCC codegen nodes, unifying them with SETCC nodes (codegen was actually often using SETCC for vector SETCC already). This ensures that various DAG combiner optimizations kick in for vector comparisons. Passes dragonegg bootstrap with no testsuite regressions (nightly testsuite as well as "make check-all"). Patch mostly by Nadav Rotem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06Fix fall outs from my recent change on how carry bit is modeled during isel.Evan Cheng
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well. Also fix isel hook to correctly set the optional operand. rdar://10073745 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139157 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01Null-initialize to shut up -Wuninitialized warnings.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-3164-bit atomic cmpxchg for ARM.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138868 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30Follow up to r138791.Evan Cheng
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to call a target hook to adjust the instruction. For ARM, this is used to adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC instructions have implicit def of CPSR (required since it now uses CPSR physical register dependency rather than "glue"). If the carry flag is used, then the target hook will *fill in* the optional operand with CPSR. Otherwise, the hook will remove the CPSR implicit def from the MachineInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138810 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30Change ARM / Thumb2 addc / adde and subc / sube modeling to use physicalEvan Cheng
register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138791 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well ↵Eli Friedman
enough to fix properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138751 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-27Silence GCC warnings and make an array const.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138706 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26Atomic load/store on ARM/Thumb.Eli Friedman
I don't really like the patterns, but I'm having trouble coming up with a better way to handle them. I plan on making other targets use the same legalization ARM-without-memory-barriers is using... it's not especially efficient, but if anyone cares, it's not that hard to fix for a given target if there's some better lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138621 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12ARM expansion of pre-indexed store pseudos should maintain memoperands.Jim Grosbach
Partial fix for rdar://9945172. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137513 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12Silence a bunch (but not all) "variable written but not read" warningsDuncan Sands
when building with assertions disabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137460 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11ARM STRH assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09ARM fix typo in pre-indexed store lowering.Jim Grosbach
rdar://9915869 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137148 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05ARM refactor indexed store instructions.Jim Grosbach
Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136978 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03New approach to r136737: insert the necessary fences for atomic ops in ↵Eli Friedman
platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing. I think this completes the basic CodeGen for atomicrmw and cmpxchg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136813 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-02ARM backend support for atomicrmw and cmpxchg with non-monotonic ordering. ↵Eli Friedman
Not especially pretty, but seems to work well enough. If this looks okay, I'll put together similar patches for Mips, PPC, and Alpha. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136737 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Add support for the 'Q' constraint.Eric Christopher
Fixes rdar://9866494 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136523 91177308-0d34-0410-b5e6-96231b3b80d8
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