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path: root/lib/Target/ARM/ARMFrameLowering.cpp
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2012-03-20Remove some redundant checks.Bob Wilson
ARMFrameLowering::hasReservedCallFrame is already checking for variable sized objects, so there's no point in checking it twice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153109 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach
With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152045 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper
size of static data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Enable ARM base pointer when calling functions with large arguments.Jakob Stoklund Olesen
When an outgoing call takes more than 2k of arguments on the stack, we don't allocate that call frame in the prolog, but adjust the stack pointer immediately before the call instead. This causes problems with the emergency spill slot because PEI can't track stack pointer adjustments on the second pass, and if the outgoing arguments are too big, SP can't be used to reach the emergency spill slot at all. Work around these problems by ensuring there is a base or frame pointer that can be used to access the emergency spill slot. <rdar://problem/10917166> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151604 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24Remove unused cl::opt, make another opt static.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151398 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu
MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-06Enable aligned NEON spilling by default.Jakob Stoklund Olesen
Experiments show this to be a small speedup for modern ARM cores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147689 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04Fix more places which should be checking for iOS, not darwin.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147513 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-24Fix Comments.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147238 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-23Experimental support for aligned NEON spills.Jakob Stoklund Olesen
ARM targets with NEON units have access to aligned vector loads and stores that are potentially faster than unaligned operations. Add support for spilling the callee-saved NEON registers to an aligned stack area using 16-byte aligned NEON loads and store. This feature is off by default, controlled by an -align-neon-spills command line option. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147211 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21Move common code into an MRI function.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147071 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07Add bundle aware API for querying instruction properties and switch the codeEvan Cheng
generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky
change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :(Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142557 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18Add support for dynamic stack realignment when in thumb1 mode.Chad Rosier
rdar://10288916 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions."Chad Rosier
to appease nightly testers. Not quite there yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-01Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact Chad Rosier
useful if an optimization assumes the stack has been realigned. Credit to Eli for his assistance. rdar://10043857 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140924 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Thumb unconditional branches are allowed in IT blocks, and therefore should ↵Owen Anderson
have a predicate operand, unlike conditional branches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Tidy up. Formatting.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25ARM fix for missing implicit operands on ldmia_ret.Andrew Trick
rdar://10005094: miscompile of 176.gcc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138568 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138566 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05ARM refactor indexed store instructions.Jim Grosbach
Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136978 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26Split am2offset into register addend and immediate addend forms, necessary ↵Owen Anderson
for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng
ARM MC code from target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-05ARM estimateStackSize() needs to account for simplified call frames.Jim Grosbach
If the function allocates reserved stack space for callee argument frames, estimateStackSize() needs to account for that, as it doesn't show up as ordinary frame objects. Otherwise, a callee with a large argument list will throw off the calculations for whether to allocate an emergency spill slot and we get assert() failures in the register scavenger. rdar://9715469 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30Refact ARM Thumb1 tMOVr instruction family.Jim Grosbach
Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions into tMOVr. There's no need to keep them separate. Giving the tMOVr instruction the proper GPR register class for its operands is sufficient to give the register allocator enough information to do the right thing directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134204 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30Thumb1 register to register MOV instruction is predicable.Jim Grosbach
Fix a FIXME and allow predication (in Thumb2) for the T1 register to register MOV instructions. This allows some better codegen with if-conversion (as seen in the test updates), plus it lays the groundwork for pseudo-izing the tMOVCC instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134197 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-17Update an insertion point iterator after replacing a return instruction with aCameron Zwarich
tail call pseudoinstruction. This fixes <rdar://problem/9624333>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133227 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-13Fix coordination for using R4 in Thumb1 as a scratch for SP restore.Jim Grosbach
The logic for reserving R4 for use as a scratch needs to match that for actually using it. Also, it's not necessary for immediate <=508, so adjust the value checked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132934 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22In Thumb2 mode, lower frame indix references to:Evan Cheng
add <rd>, sp, #<imm8> ldr <rd>, [sp, #<imm8>] When the offset from sp is multiple of 4 and in range of 0-1020. This saves code size by utilizing 16-bit instructions. rdar://9321541 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129971 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches.Jim Grosbach
Also more cleanly separate the ARM vs. Thumb functionality. Previously, the encoding would be incorrect for some Thumb instructions (the indirect calls). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127637 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05Preliminary support for ARM frame save directives emission via MI flags.Anton Korobeynikov
This is just very first approximation how the stuff should be done (e.g. ARM-only for now). More to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127101 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-25Fix typo.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126467 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-25Each prologue may have multiple vpush instructions to store callee-savedEvan Cheng
D registers since the vpush list may not have gaps. Make sure the stack adjustment instruction isn't moved between them. Ditto for vpop in epilogues. Sorry, can't reduce a small test case. rdar://9043312 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126457 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-14Remove unused bitvectors that record ARM callee-saved registers.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125534 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-25Don't merge restore with tail call instruction.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124167 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-18Remove unused variables found by gcc-4.6's -Wunused-but-set-variable.Jeffrey Yasskin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123707 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-16Spill R4 if it's going to be used to restore SP from FP.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123567 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-13Teach frame lowering to ignore debug values after the terminators.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123399 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-13Tidy comments, indentation, and 80-column violations.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123397 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-11Clean up ARM subtarget code by using Triple ADT.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123276 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10Expand on the safeness of restoring the sp from the fp a bit more.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123193 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov
and fixes here and there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
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