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enabled for all targets. Non-X86 targets should not have this behavior
enabled by default.
Joerg, if you would like to resubmit with the behavior conditionalized to be
X86-ELF only, that's fine.
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Fixes PR9292.
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it to ignore valid uses of FS and GS as additional
base registers in address computations. Added a test
case for this.
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r124468. Patch by Rafael Avila de Espindola!
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parser.
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Radar 9012638.
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independent vectors.
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PR9245.
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the right thing and stop trying to copy it. Fixes PR8944.
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This is submitted by Joerg Sonnenberger and fixes his PR8685.
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section.
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Now, Syntax is only used as a tie-breaker if the Arch
matches. Previously, a request for x86_64 disassembler followed by the
i386 disassembler in a single process would return the cached x86_64
disassembler. Fixes <rdar://problem/8958982>
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Sonnenberger.
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failures with relocations.
The code committed is a first cut at compatibility for emitted relocations in
ELF .o.
Why do this? because existing ARM tools like emitting relocs symbols as
explicit relocations, not as section-offset relocs.
Result is that with these changes,
1) relocs are now substantially identical what to gcc outputs.
2) larger apps (including many spec2k tests) compile, cross-link, and pass
Added reminder fixme to tests for future conversion to .s form.
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5 to match the current doc.
Added FIXME reminder Make it really configurable later.
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(yes, this is different from R_ARM_CALL)
- Adds a new method getARMBranchTargetOpValue() which handles the
necessary distinction between the conditional and unconditional br/bl
needed for ARM/ELF
At least for ARM mode, the needed fixup for conditional versus unconditional
br/bl is identical, but the ARM docs and existing ARM tools expect this
reloc type...
Added a few FIXME's for future naming fixups in ARMInstrInfo.td
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unbreaks some ARM tests.
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all lead to a silent miscompilation of code.
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as well as register number.
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encoding. It's up to the individual back-ends to convert it to their preferred
representation when printing.
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* If the name is a single string, we remove the quotes
* If the name starts without a quote, we include any quotes in the name
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Add support for SHT_X86_64_UNWIND.
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- Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first.
- Added support for Thumb2 :lower16: and :upper16: fix up.
- Added :upper16: and :lower16: relocation support to mach-o object writer.
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So it's possible for some bits of every 8 bits to be encoded already, and the rest still needs to be fixed up.
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in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.
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R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)
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and fixes here and there.
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