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2012-09-09LiveVariables: Compute a set of defs and kills to speed up updating LV ↵Benjamin Kramer
during critical edge splitting. Previously we checked if the register is def'd in a block via the def/use list a nd walked the list of kills to check if the register is killed in a block. Both of these checks can be made much cheaper by walking the block first and recording all defs and kills. This reduces the compile time of the test case from PR13651 from 40s to 15s at -O2. The compile time is still dominated by LV updating but now the main culprit is SparseBitVector's slowness. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163478 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07Fix alignment of .comm and .lcomm on mingw32.Benjamin Kramer
For some reason .lcomm uses byte alignment and .comm log2 alignment so we can't use the same setting for both. Fix this by reintroducing the LCOMM enum. I verified this against mingw's gcc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163420 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07Fix indent.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163416 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07Update function names to conform to guidelines. No functional change intended.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163401 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07MC: Overhaul handling of .lcommBenjamin Kramer
- Darwin lied about not supporting .lcomm and turned it into zerofill in the asm parser. Push the zerofill-conversion down into macho-specific code. - This makes the tri-state LCOMMType enum superfluous, there are no targets without .lcomm. - Do proper error reporting when trying to use .lcomm with alignment on a target that doesn't support it. - .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2. - Fixes PR13755 (.lcomm crashes on ELF). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163395 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07Stop emitting lifetime region info when stack coloring is not enabled in O0Michael Liao
- this should fix PR13780 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163370 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Release build: guard dump functions with "ifndef NDEBUG"Manman Ren
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163339 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Allow overlaps between virtreg and physreg live ranges.Jakob Stoklund Olesen
The RegisterCoalescer understands overlapping live ranges where one register is defined as a copy of the other. With this change, register allocators using LiveRegMatrix can do the same, at least for copies between physical and virtual registers. When a physreg is defined by a copy from a virtreg, allow those live ranges to overlap: %CL<def> = COPY %vreg11:sub_8bit; GR32_ABCD:%vreg11 %vreg13<def,tied1> = SAR32rCL %vreg13<tied0>, %CL<imp-use,kill> We can assign %vreg11 to %ECX, overlapping the live range of %CL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163336 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Handle overlapping regunit intervals in LiveIntervals::addKillFlags().Jakob Stoklund Olesen
We will soon allow virtual register live ranges to overlap regunit live ranges when the physreg is defined as a copy of the virtreg: %EAX = COPY %vreg5 FOO %vreg5 BAR %EAX<kill> There is no real interference since %vreg5 and %EAX have the same value where they overlap. This patch prevents addKillFlags from adding virtreg kill flags to FOO where the assigned physreg is overlapping the virtual register live range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163335 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Clear kill flags while computing live ranges.Jakob Stoklund Olesen
Kill flags are difficult to maintain, and liveness queries are better handled by live intervals. Kill flags are reinserted after register allocation by addKillFlags(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163334 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Dont cast away const needlessly. Found by gcc48 -Wcast-qual.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163324 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Disable stack coloring by default in order to resolve the i386 failures.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163316 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Fix a few old-GCC warnings. No functional change.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163309 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Add a new optimization pass: Stack Coloring, that merges disjoint static ↵Nadav Rotem
allocations (allocas). Allocas are known to be disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163299 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05[ms-inline asm] Use the asm dialect from the MI to set the parser dialect.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163273 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05Cleanup a few magic numbers.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163263 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05Stop casting away const qualifier needlessly.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163258 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05[ms-inline asm] We only need one bit to represent the AsmDialect in theChad Rosier
MachineInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163257 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05Constify this properly. Found by gcc48 -Wcast-qual.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163256 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05Constify SDNodeIterator an stop its only non-const user being cast strippedRoman Divacky
of its constness. Found by gcc48 -Wcast-qual. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163254 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05[ms-inline asm] Propagate the asm dialect into the MachineInstr representation.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163243 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05Remove unused typedefs gcc4.8 warns about.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163225 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05Fixed the DAG combiner to better handle the folding of AND nodes for vector ↵Silviu Baranga
types. The previous code was making the assumption that the length of the bitmask returned by isConstantSplat was equal to the size of the vector type. Now we first make sure that the splat value has at least the length of the vector lane type, then we only use as many fields as we have available in the splat value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163203 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05Reorder the comments of EmitExceptionTable.Logan Chien
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163194 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05Convert vextracti128/vextractf128 intrinsics to extract_subvector at DAG ↵Craig Topper
build time. Similar was previously done for vinserti128/vinsertf128. Add patterns for folding these extract_subvectors with stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163192 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Search the whole instruction for tied operands.Jakob Stoklund Olesen
Implicit uses can be dynamically tied to defs. This will soon be used for predicated instructions on ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163177 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Typo.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163154 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Actually use the MachineOperand field for isRegTiedToDefOperand().Jakob Stoklund Olesen
The MachineOperand::TiedTo field was maintained, but not used. This patch enables it in isRegTiedToDefOperand() and isRegTiedToUseOperand() which are the actual functions use by the register allocator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163153 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Move tie checks into MachineVerifier::visitMachineOperand.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163152 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Allow tied uses and defs in different orders.Jakob Stoklund Olesen
After much agonizing, use a full 4 bits of precious MachineOperand space to encode this. This uses existing padding, and doesn't grow MachineOperand beyond its current 32 bytes. This allows tied defs among the first 15 operands on a normal instruction, just like the current MCInstrDesc constraint encoding. Inline assembly needs to be able to tie more than the first 15 operands, and gets special treatment. Tied uses can appear beyond 15 operands, as long as they are tied to a def that's in range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163151 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Generic Bypass Slow DivPreston Gurd
- CodeGenPrepare pass for identifying div/rem ops - Backend specifies the type mapping using addBypassSlowDivType - Enabled only for Intel Atom with O2 32-bit -> 8-bit - Replace IDIV with instructions which test its value and use DIVB if the value is positive and less than 256. - In the case when the quotient and remainder of a divide are used a DIV and a REM instruction will be present in the IR. In the non-Atom case they are both lowered to IDIVs and CSE removes the redundant IDIV instruction, using the quotient and remainder from the first IDIV. However, due to this optimization CSE is not able to eliminate redundant IDIV instructions because they are located in different basic blocks. This is overcome by calculating both the quotient (DIV) and remainder (REM) in each basic block that is inserted by the optimization and reusing the result values when a subsequent DIV or REM instruction uses the same operands. - Test cases check for the presents of the optimization when calculating either the quotient, remainder, or both. Patch by Tyler Nowicki! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163150 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03IRBuilderify the SjlLjEHPrepare pass.Benjamin Kramer
No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163115 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03When updating live range endpoints, make sure to preserve the early clobber bit.Lang Hames
Fixs PR13719. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163107 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-02Fix a typo.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163094 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-02Generate better select code by allowing the target to use scalar select, and ↵Nadav Rotem
not sign-extend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-01Only legalise a VSELECT in to bitwise operations if the vector mask bool is ↵Pete Cooper
zeros or all ones. A vector bool with just ones isn't suitable for masking with. No test case unfortunately as i couldn't find a target which fit all the conditions needed to hit this code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-01Revert "Take account of boolean vector contents when promoting a build ↵Pete Cooper
vector from i1 to some other type. rdar://problem/12210060" This reverts commit 5dd9e214fb92847e947f9edab170f9b4e52b908f. Thanks to Duncan for explaining how this should have been done. Conflicts: test/CodeGen/X86/vec_select.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163064 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-01Fix typo.Logan Chien
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163059 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-01Teach DAG combine a number of tricks to simplify FMA expressions in ↵Owen Anderson
fast-math mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163051 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-01Fix typoMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163049 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31Add MachineInstr::tieOperands, remove setIsTied().Jakob Stoklund Olesen
Manage tied operands entirely internally to MachineInstr. This makes it possible to change the representation of tied operands, as I will do shortly. The constraint that tied uses and defs must be in the same order was too restrictive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163021 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31Use CloneMachineInstr to make a new MI in commuteInstruction to make the ↵Craig Topper
code tolerant of instructions with more than two input operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163000 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31Don't enforce ordered inline asm operands.Jakob Stoklund Olesen
I was too optimistic, inline asm can have tied operands that don't follow the def order. Fixes PR13742. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162998 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30Take account of boolean vector contents when promoting a build vector from ↵Pete Cooper
i1 to some other type. rdar://problem/12210060 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30Teach the DAG combiner to turn chains of FADDs (x+x+x+x+...) into FMULs by ↵Owen Anderson
constants. This is only enabled in unsafe FP math mode, since it does not preserve rounding effects for all such constants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162956 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30Currently targets that do not support selects with scalar conditions and ↵Nadav Rotem
vector operands - scalarize the code. ARM is such a target because it does not support CMOV of vectors. To implement this efficientlyi, we broadcast the condition bit and use a sequence of NAND-OR to select between the two operands. This is the same sequence we use for targets that don't have vector BLENDs (like SSE2). rdar://12201387 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162926 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30Don't use MCInstrDesc flags for implicit operands.Jakob Stoklund Olesen
When a MachineInstr is constructed, its implicit operands are added first, then the explicit operands are inserted before the implicits. MCInstrDesc has oprand flags like early clobber and operand ties that apply to the explicit operands. Don't look at those flags when the implicit operands are first added in the explicit operands's positions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162910 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30Add FMA to switch statement in VectorLegalizer::LegalizeOp so that it can be ↵Craig Topper
expanded when it isn't legal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162894 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30Add support for FMA to WidenVectorResult.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162893 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29Verify the order of tied operands in inline asm.Jakob Stoklund Olesen
When there are multiple tied use-def pairs on an inline asm instruction, the tied uses must appear in the same order as the defs. It is possible to write an LLVM IR inline asm instruction that breaks this constraint, but there is no reason for a front end to emit the operands out of order. The gnu inline asm syntax specifies tied operands as a single read/write constraint "+r", so ouf of order operands are not possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162878 91177308-0d34-0410-b5e6-96231b3b80d8
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