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2012-11-19Handle mixed normal and early-clobber defs on inline asm.Jakob Stoklund Olesen
PR14376. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168320 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-19Move else onto line with preceding closing brace.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168294 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-17Broaden isSchedulingBoundary to check aliases of SP.Andrew Trick
On PPC the stack pointer is X1, but ADJCALLSTACK writes R1. Fixes PR14315: Register regmask dependency problem with misched. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168248 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-17Mark FP_EXTEND form v2f32 to v2f64 as "expand" for ARM NEON. Patch by Pete ↵Eli Friedman
Couperus. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168240 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16Use array_pod_sort instead of std::sort.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168203 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16Remove conditions from 'else if' that were guaranteed by preceding 'if'.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168191 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16Factor out the final FADD that's common to multiple code paths in the ↵Craig Topper
visitLog* functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168183 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16Factor some common code to reduce compile size.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168143 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Mark FP_ROUND for converting NEON v2f64 to v2f32 as expand. Add a missingEli Friedman
case to vector legalization so this actually works. Patch by Pete Couperus. Fixes PR12540. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168107 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Use std::stable_sort instead of std::sort when sorting stack slotsUlrich Weigand
to guarantee deterministic code generation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168074 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15[reg scavenger] Fix the isUsed/isAliasUsed functions so as to not report a falseChad Rosier
positive. In this particular case, R6 was being spilled by the register scavenger when it was in fact dead. The isUsed function reported R6 as used because the R6_R7 alias was reserved (due to the fact that we've reserved R7 as the FP). The solution is to only check if the original register (i.e., R6) isReserved and not the aliases. The aliases are only checked to make sure they're available. The test case is derived from one of the nightly tester benchmarks and is rather intractable and difficult to reproduce, so I haven't included it. rdar://12592448 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168054 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Merge commit '08e9cb46feb0c8e08e3d309a0f9fd75a04ca54fb'Derek Schuff
(svn r167699, also the 3.2 branch point) Conflicts: lib/Target/X86/X86Subtarget.cpp
2012-11-15Fix indeterminism in MI scheduler DAG construction.Sergei Larin
Similarly to several recent fixes throughout the code replace std::map use with the MapVector. Add find() method to the MapVector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168051 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Add llvm.ceil, llvm.trunc, llvm.rint, llvm.nearbyint intrinsics.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168025 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Fix an obvious merge bug in -join-globalcopies (disabled).Andrew Trick
Jakub Staszak spotted this in review. I don't notice these things until I manually rerun benchmarks. But reducing unit tests is a very high priority. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168021 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Use reserve() to avoid vector reallocation.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167991 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14canJoinPhys method doesn't modify CoalescerPair. Make it const.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167972 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Remove dead code.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167970 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Fix really stupid ARM EHABI info generation bug: we should not emitAnton Korobeynikov
eh table and handler data if there are no landing pads in the function. Patch by Logan Chien with some cleanups from me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167945 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Add newlines to end of debug messages.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167913 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Handle DAG CSE adding new uses during ReplaceAllUsesWith. Fixes PR14333.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167912 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Merge commit 'be02a90de17f857ba65bbd8a11653ca1bad30adc'Derek Schuff
Conflicts: lib/Target/Mips/MipsISelLowering.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrFormats.td
2012-11-14Use TARGET2 relocation for TType references on ARM.Anton Korobeynikov
Do some cleanup of the code while here. Inspired by patch by Logan Chien! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167904 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Revert "Use the 'count' attribute instead of the 'upper_bound' attribute."Eric Christopher
temporarily as it is breaking the gdb bots. This reverts commit r167806/e7ff4c14b157746b3e0228d2dce9f70712d1c126. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167886 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Revert -join-splitedges to a boolean cmd line option.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167880 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13The MachineScheduler does not currently require JoinSplitEdges.Andrew Trick
This option will eventually either be enabled unconditionally or replaced by a more general live range splitting optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167879 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13[MC][COFF] Emit weak symbols to the correct section. Patch by Dmitry Puzirev!Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167877 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Do not consider a machine instruction that uses and defines the sameUlrich Weigand
physical register as candidate for common subexpression elimination in MachineCSE. This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc caused by MachineCSE invalidly merging two separate DYNALLOC insns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167855 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Fix -join-splitedges: my previous "cleanup" broke it.Andrew Trick
Working on reducing unit tests. This won't be enabled unless a subtarget enables misched. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167851 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Codegen support for arbitrary vector getelementptrs.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167830 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13misched: Allow subtargets to enable misched and dependent options.Andrew Trick
This allows me to begin enabling (or backing out) misched by default for one subtarget at a time. To run misched we typically want to: - Disable SelectionDAG scheduling (use the source order scheduler) - Enable more aggressive coalescing (until we decide to always run the coalescer this way) - Enable MachineScheduler pass itself. Disabling PostRA sched may follow for some subtargets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167826 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Added RegisterCoalescer support for joining global copies first.Andrew Trick
This adds the -join-globalcopies option which can be enabled by default once misched is also enabled. Ideally, the register coalescer would be able to split local live ranges in a way that produces copies that can be easily resolved by the scheduler. Until then, this heuristic should be good enough to at least allow the scheduler to run after coalescing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167825 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13misched: Don't consider artificial edges weak edges.Andrew Trick
For now be more conservative in case other out-of-tree schedulers rely on the old behavior of artificial edges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167808 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Use the 'count' attribute instead of the 'upper_bound' attribute.Bill Wendling
If we have a type 'int a[1]' and a type 'int b[0]', the generated DWARF is the same for both of them because we use the 'upper_bound' attribute. Instead use the 'count' attrbute, which gives the correct number of elements in the array. <rdar://problem/12566646> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167806 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Cleanup the main RegisterCoalescer loop.Andrew Trick
Block priorities still apply outside loops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167793 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12Cleanup -join-splitedges. Make the loop more obvious.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167785 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12Add an option to enable prototype "fission" capabilities and debug changes.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167765 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12Added a temporary option to avoid critical edges splitting.Andrew Trick
This teaches the register coalescer to be less prone to split critical edges. I am currently benchmarking this with the new (post-coalescer) scheduler. I plan to enable this by default and remove the option as soon as misched is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167758 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12misched: rename interfaceto avoid gcc warningsAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167753 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12misched: Target-independent support for MacroFusion.Andrew Trick
Uses the infrastructure from r167742 to support clustering instructure that the target processor can "fuse". e.g. cmp+jmp. Next step: target hook implementations with test cases, and enable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167744 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12misched: Target-independent support for load/store clustering.Andrew Trick
This infrastructure is generally useful for any target that wants to strongly prefer two instructions to be adjacent after scheduling. A following checkin will add target-specific hooks with unit tests. Then this feature will be enabled by default with misched. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167742 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12misched: Infrastructure for weak DAG edges.Andrew Trick
This adds support for weak DAG edges to the general scheduling infrastructure in preparation for MachineScheduler support for heuristics based on weak edges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167738 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09Fix assertions in updateRegMaskSlots().Jakob Stoklund Olesen
The RegMaskSlots contains 'r' slots while NewIdx and OldIdx are 'B' slots. This broke the checks in the assertions. This fixes PR14302. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167625 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09Silence GCC warning about falling off the end of a non-void function.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167618 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07misched: Heuristics based on the machine model.Andrew Trick
misched is disabled by default. With -enable-misched, these heuristics balance the schedule to simultaneously avoid saturating processor resources, expose ILP, and minimize register pressure. I've been analyzing the performance of these heuristics on everything in the llvm test suite in addition to a few other benchmarks. I would like each heuristic check to be verified by a unit test, but I'm still trying to figure out the best way to do that. The heuristics are still in considerable flux, but as they are refined we should be rigorous about unit testing the improvements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167527 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07misched: handle on-the-fly regpressure queries better for 2-addrAndrew Trick
instructions without relying on liveintervals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167526 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07Add comment describing what's going on here.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167525 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07When we're updating the subprogram scope DIE, we want to determine if we'reBill Wendling
updating an abstract DIE or not. If we are, then we use that. Its children will be added on later, as well as the object pointer attribute. Otherwise, this function may be called with a concrete DIE twice and adding the children and object pointer attribute to it twice. <rdar://problem/12401423&12600340> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167524 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-06[regallocfast] Make sure the MachineRegisterInfo is aware of clobbers from aChad Rosier
register masks. This is an obvious and necessary fix for a soon to be committed patch. No test case possible at this time. Reviewed by Jakob. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167498 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-06Remove ARM constant patch that affected x86 upstreamDavid Sehr
The patch I removed was apparently put in to keep constant islands from growing past 16 bytes, which included a guard word at the beginning. Since we do not generate constant islands, I am removing this. BUG= http://code.google.com/p/nativeclient/issues/detail?id=3125 Review URL: https://codereview.chromium.org/11368105
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