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The *Impl class no longer serves a purpose now that the super-class
implementation is in CodeGen.
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The Target library is not allowed to depend on the large CodeGen
library, but the TRI and TII classes provide abstract interfaces that
require both caller and callee to link to CodeGen.
The implementation files for these classes provide default
implementations of some of the hooks. These methods may need to
reference CodeGen, so they belong in that library.
We already have a number of methods implemented in the
TargetInstrInfoImpl sub-class because of that. I will merge that class
into the parent next.
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the coding standard would like.
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Conflicts:
lib/CodeGen/AsmPrinter/DwarfDebug.cpp
lib/CodeGen/AsmPrinter/DwarfDebug.h
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
lib/Target/Mips/MipsISelDAGToDAG.cpp
lib/Target/Mips/MipsInstrFPU.td
lib/Target/Mips/MipsSubtarget.cpp
lib/Target/Mips/MipsSubtarget.h
lib/Target/X86/X86MCInstLower.cpp
tools/Makefile
tools/llc/llc.cpp
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boundaries.
Given the following case:
BB0
%vreg1<def> = SUBrr %vreg0, %vreg7
%vreg2<def> = COPY %vreg7
BB1
%vreg10<def> = SUBrr %vreg0, %vreg2
We should be able to CSE between SUBrr in BB0 and SUBrr in BB1.
rdar://12462006
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argument. Instead, use a pair of .local and .comm directives.
This avoids spurious differences between binaries built by the
integrated assembler vs. those built by the external assembler,
since the external assembler may impose alignment requirements
on .lcomm symbols where the integrated assembler does not.
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and O0 + debug codegen.
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add a TODO for starting.
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r168627), we no longer need to call the freezeReservedRegs() function a second
time. Previously, this pass was conservatively adding the FP to the set of
reserved registers, requiring the second update to the reserved registers.
rdar://12719844
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r168627), we no longer need to call the freezeReservedRegs() function a second
time. Previously, this pass was conservatively adding the FP to the set of
reserved registers, requiring the second update to the reserved registers.
rdar://12719844
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earlier before IsExp10 could be set to true.
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called at the start of the function and captured in a local variable.
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isOperationLegal. Thanks to Craig Topper for pointing this out.
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around.
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everything else underneath.
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+ Take account of clobbers
+ Give outputs priority over inputs since they happen later.
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the zero GV check inside, so we won't forget it at the caller side.
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It turned out that ARM wants different layout of type infos.
This is yet another patch in attempt to fix PR7187
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depending on them being emitted before the text and/or data
sections and testing didn't uncover any.
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