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2012-12-06change MCContext to work on the doInitialization/doFinalization modelPedro Artigas
reviewed by Evan Cheng <evan.cheng@apple.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169456 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05RegPressureTracker::dump(): Remove unnecessary argument.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169443 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05RegisterPressureTracker: fix findUseBetween to handle DebugValueAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169427 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05RegisterPressureTracker: unify virtual registers and physical regunits.Andrew Trick
Now that live register units are tracked individually, the code can be simplified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169426 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05RegisterPresssureTracker: Track live physical register by unit.Andrew Trick
This is much simpler to reason about, more efficient, and fixes some corner cases involving implicit super-register defs. Fixed rdar://12797931. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169425 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05Remove unused MachineInstr constructors.Jakob Stoklund Olesen
A MachineInstr can only ever be constructed by CreateMachineInstr() and CloneMachineInstr(), and those factories don't use the removed constructors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169395 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05- Added calls to doInitialization/doFinalization to immutable passesPedro Artigas
- fixed ordering of calls to doFinalization to be the reverse of the pass run order due to potential dependencies - fixed machine module info to operate in the doInitialization/doFinalization model, also fixes some FIXMEs reviewed by Evan Cheng <evan.cheng@apple.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169391 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05Added RegisterPressureTracker::dump() for debugging.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169359 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04Speed up the AllocationOrder class a bit.Jakob Stoklund Olesen
Allow the central functions to be inlined, and use the argumentless isHint() function when possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169319 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04Comment change made in r169304 as requested by Eric Christopher.David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169315 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04Use the 'count' attribute to calculate the upper bound of an array.Bill Wendling
The count attribute is more accurate with regards to the size of an array. It also obviates the upper bound attribute in the subrange. We can also better handle an unbound array by setting the count to -1 instead of the lower bound to 1 and upper bound to 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169312 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04Reapply r160148 (reverted in r163570) fixing spurious breakpoints in modern GDBDavid Blaikie
This reapplies the fix for PR13303 now with more justification. Based on my execution of the GDB 7.5 test suite this results in: expected passes: 16101 -> 20890 (+30%) unexpected failures: 4826 -> 637 (-77%) There are 23 checks that used to pass and now fail. They are all in gdb.reverse. Investigating a few looks like they were accidentally passing due to extra breakpoints being set by this bug. They're generally due to the difference in end location between gcc and clang, the test suite is trying to set breakpoints on the closing '}' that clang doesn't associate with any instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169304 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth
missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169224 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04Add a 'count' field to the DWARF subrange.Bill Wendling
The count field is necessary because there isn't a difference between the 'lo' and 'hi' attributes for a one-element array and a zero-element array. When the count is '0', we know that this is a zero-element array. When it's >=1, then it's a normal constant sized array. When it's -1, then the array is unbounded. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169218 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04Simplify code. No functionality change.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169198 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04Stack Alignment: when creating stack objects in MachineFrameInfo, make sureManman Ren
the alignment is clamped to TargetFrameLowering.getStackAlignment if the target does not support stack realignment or the option "realign-stack" is off. This will cause miscompile if the address is treated as aligned and add is replaced with or in DAGCombine. Added a bool StackRealignable to TargetFrameLowering to check whether stack realignment is implemented for the target. Also added a bool RealignOption to MachineFrameInfo to check whether the option "realign-stack" is on. rdar://12713765 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169197 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04Use dyn_cast instead of isa and cast. No functionality change.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169196 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04Remove VirtRegMap::getRegAllocPref().Jakob Stoklund Olesen
Now that there can be multiple hint registers from targets, it doesn't make sense to have a function that returns 'the' preferred register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169190 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04Use MRI::getSimpleHint() instead of getRegAllocPref() in remaining cases.Jakob Stoklund Olesen
Targets can provide multiple hints now, so getRegAllocPref() doesn't make sense any longer because it only returns one preferred register. Replace it with getSimpleHint() in the remaining heuristics. This function only git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169188 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04Stack Alignment: move functions from header file MachineFrameInfo.h.Manman Ren
No functional change for this commit. The follow-up patch will add more stuff to these functions. rdar://12713765 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169186 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03Add VirtRegMap::hasKnownPreference().Jakob Stoklund Olesen
Virtual registers with a known preferred register are prioritized by RAGreedy. This function makes the condition explicit without depending on getRegAllocPref(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169179 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03Use the new getRegAllocationHints() hook from AllocationOrder.Jakob Stoklund Olesen
This simplifies the hinting code quite a bit while making the targets easier to write at the same time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169173 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03moves doInitialization and doFinalization to the Pass class and removes some ↵Pedro Artigas
unreachable code in MachineModuleInfo reviewed by Evan Cheng <evan.cheng@apple.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169164 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03Add a new hook for providing register allocator hints more flexibly.Jakob Stoklund Olesen
The TargetRegisterInfo::getRegAllocationHints() function is going to replace the existing mechanisms for providing target-dependent hints to the register allocator: ResolveRegAllocHint() and getRawAllocationOrder(). The new hook is more flexible because it allows the target to provide multiple preferred candidate registers for each virtual register, and it is easier to use because targets are not required to return a reference to a constant array like getRawAllocationOrder(). An optional VirtRegMap argument can be used to provide target-dependent hints that depend on the provisional assignments of other virtual registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169154 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03Fix PR12942: Allow two CUs to be generated from the same source file.Eli Bendersky
Thanks Eric for the review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169142 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03Use the new script to sort the includes of every file under lib.Chandler Carruth
Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-02Allow merging multiple store sequences on the same chain.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169111 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-01misched: Fix RegisterPressureTracker handling of DebugVals.Andrew Trick
Assertion failed: (TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker"). rdar://12790302. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169072 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-01misched: Fix the DAG builder to handle an undef operand at ExitSU.Andrew Trick
Assertion failed: (VNI && "No value to read by operand") rdar://12790267. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169071 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-01misched: Fix LiveInterval update to better handle DebugVal.Andrew Trick
Assertion failed: (itr != mi2iMap.end() && "Instruction not found in maps.") rdar://12777252. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169070 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-01misched: fix RegionBegin when DebugValues get shuffled to the top.Andrew Trick
assert (RemainingInstrs == 0 && "Instruction count mismatch!") rdar://12776937. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169069 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-01Simplify REG_SEQUENCE lowering.Jakob Stoklund Olesen
The TwoAddressInstructionPass takes the machine code out of SSA form by expanding REG_SEQUENCE instructions into copies. It is no longer necessary to rewrite the registers used by a REG_SEQUENCE instruction because the new coalescer algorithm can do it now. REG_SEQUENCE is just converted to a sequence of sub-register copies now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169067 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-30Add some first skeleton work for the DWARF5 Fission proposal. EmitEric Christopher
part of the compile unit CU and start separating out information into the various sections that will be pulled out later. WIP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169061 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-30Convert COPY instructions into KILLs if they have implicit defs.Jakob Stoklund Olesen
MachineCopyPropagation doesn't understand super-register liveness well enough to be able to remove implicit defs of super-registers. This fixes a problem in ARM/2012-01-26-CopyPropKills.ll that is exposed by an future TwoAddressInstructionPass change. The KILL instructions are removed before the machine code is emitted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169060 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-30Replace r168930 with a more reasonable patch.Bill Wendling
The original patch removed a bunch of code that the SjLjEHPrepare pass placed into the entry block if all of the landing pads were removed during the CodeGenPrepare class. The more natural way of doing things is to run the CGP *before* we run the SjLjEHPrepare pass. Make it so! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169044 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-30Use isOSNaCl and minimize some LOCALMODsDavid Sehr
Another try after fumble-fingering git repos for https://codereview.chromium.org/11428097/ BUG= Review URL: https://codereview.chromium.org/11415231
2012-11-29More comment.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168952 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29Make compilation unit number change local to NaClDavid Sehr
Debug compilation unit numbers were different from upstream because NaCl observed an issue with the same object file being compiled twice, creating duplicate symbol names. To handle this, NaCl disambiguates symbols by more than just the path to the compilation unit. Make this properly conditional on NaCl, and hope we can upstream a fix someday to remove the need. BUG= http://code.google.com/p/nativeclient/issues/detail?id=1711 Review URL: https://codereview.chromium.org/11308216
2012-11-29Cleanup recent addition of DAGTypeLegalizer::SplitVecOp_VSELECTJustin Holewinski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168932 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29misched: Recompute priority queue when DFSResults are updated.Benjamin Kramer
This was found by MSVC10's STL debug mode on a test from the test suite. Sadly std::is_heap isn't standard so there is no way to assert this without writing our own heap verify, which looks like overkill to me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168885 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29Teach the legalizer how to handle operands for VSELECT nodesJustin Holewinski
If we need to split the operand of a VSELECT, it must be the mask operand. We split the entire VSELECT operand with EXTRACT_SUBVECTOR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168883 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29Allow targets to prefer TypeSplitVector over TypePromoteInteger when ↵Justin Holewinski
computing the legalization method for vectors For some targets, it is desirable to prefer scalarizing <N x i1> instead of promoting to a larger legal type, such as <N x i32>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168882 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29Use MCPhysReg for RegisterClassInfo allocation orders.Jakob Stoklund Olesen
This saves a bit of memory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168852 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29Avoid rewriting instructions twice.Jakob Stoklund Olesen
This could cause miscompilations in targets where sub-register composition is not always idempotent (ARM). <rdar://problem/12758887> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168837 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29When combining consecutive stores allow loads in between the stores, if the ↵Nadav Rotem
loads do not alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168832 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-28Make the LiveRegMatrix analysis available to targets.Jakob Stoklund Olesen
No functional change, just moved header files. Targets can inject custom passes between register allocation and rewriting. This makes it possible to tweak the register allocation before rewriting, using the full global interference checking available from LiveRegMatrix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168806 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-28misched: Analysis that partitions the DAG into subtrees.Andrew Trick
This is a simple, cheap infrastructure for analyzing the shape of a DAG. It recognizes uniform DAGs that take the shape of bottom-up subtrees, such as the included matrix multiplication example. This is useful for heuristics that balance register pressure with ILP. Two canonical expressions of the heuristic are implemented in scheduling modes: -misched-ilpmin and -misched-ilpmax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168773 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-28misched: rename ScheduleDAGILP to ScheduleDFS to prepare for other heuristics.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168772 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-28misched: better alias analysis.Andrew Trick
This fixes a hole in the "cheap" alias analysis logic implemented within the DAG builder itself, regardless of whether proper alias analysis is enabled. It now handles this pattern produced by LSR+CodeGenPrepare. %sunkaddr1 = ptrtoint * %obj to i64 %sunkaddr2 = add i64 %sunkaddr1, %lsr.iv %sunkaddr3 = inttoptr i64 %sunkaddr2 to i32* store i32 %v, i32* %sunkaddr3 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168768 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-28misched: Debug output fix. Use an always valid iterator.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168767 91177308-0d34-0410-b5e6-96231b3b80d8
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