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2011-06-27During bottom up fast-isel, instructions emitted to materalize registers are ↵Devang Patel
at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27The index stored in the RegDefIter is one after the current index. When ↵Owen Anderson
getting the index, decrement it so that it points to the current element. Fixes an off-by-one bug encountered when trying to make use of MVT::untyped. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133923 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27pre-RA-sched: Cleanup register pressure tracking.Andrew Trick
Removed the check that peeks past EXTRA_SUBREG, which I don't think makes sense any more. Intead treat it as a normal register def. No significant affect on x86 or ARM benchmarks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133917 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Track live-out physical registers in MachineDCE.Jakob Stoklund Olesen
Patch by Sanjoy Das! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133910 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Distinguish early clobber output operands from clobbered registers.Jakob Stoklund Olesen
Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we now use two different asm operand kinds. The new Kind_Clobber is treated identically to the old Kind_RegDefEarlyClobber for now, but x87 floating point stack inline assembly does care about the difference. This will pop a register off the stack: asm("fstp %st" : : "t"(x) : "st"); While this will pop the input and push an output: asm("fst %st" : "=&t"(r) : "t"(x)); We need to know if ST0 was a clobber or an output operand, and we can't depend on <dead> flags for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133902 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Decode and pretty print inline asm operand descriptors.Jakob Stoklund Olesen
The INLINEASM MachineInstrs have an immediate operand describing each original inline asm operand. Decode the bits in MachineInstr::print() so it is easier to read: INLINEASM <es:rorq $1,$0>, $0:[regdef], %vreg0<def>, %vreg1<def>, $1:[imm], 1, $2:[reguse] [tiedto:$0], %vreg2, %vreg3, $3:[regdef-ec], %EFLAGS<earlyclobber,imp-def> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133901 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-26Remove unused methods.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133900 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-26There is only one register coalescer. Merge it into the base class andRafael Espindola
remove the analysis group. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133899 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-26Merge SimpleRegisterCoalescing.cpp into RegisterCoalescer.cpp.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133897 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-26merge SimpleRegisterCoalescing.h into RegisterCoalescer.h.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133896 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-26Move RegisterCoalescer.h to lib/CodeGen.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-26Remove unnecessary wrapper.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133886 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24The scheduler needs to be aware on the existence of untyped nodes when it ↵Owen Anderson
performs type propagation for EXTRACT_SUBREG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133838 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Handle debug info for i128 constants.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133821 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24SimplifyRafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133798 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Now that bb with phis are not considered simple, duplicate them even ifRafael Espindola
we cannot duplicate to every predecessor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133797 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Simplify now that blocks with phis are not considered simple.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133793 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Starting to refactor Target to separate out code that's needed to fully describeEvan Cheng
target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23Use the presence of the __compact_unwind section to indicate that a targetBill Wendling
supports compact unwind info instead of having a separate flag indicating this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133685 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23Move more logic to shouldTailDuplicate and only duplicate regular bb beforeRafael Espindola
register allocation if it has a indirectbr or if we can duplicate it to every predecessor. This fixes the SingleSource/Benchmarks/Shootout-C++/matrix.cpp regression but keeps the previous improvements to sunspider. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22Add a flag that indicates whether a target supports compact unwind info or not.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22Reenable tail duplication of bb with just an unconditional jump, butRafael Espindola
don't remove blocks that have their address taken. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133659 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22Add a __LD,__compact_unwind section.Bill Wendling
If the linker supports it, this will hold the CIE and FDE information in a compact format. The implementation of the compact unwinding emission is coming soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133658 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22Revert r133607. This is causing failures in the Clang gccTestSuite.Chad Rosier
Specifically, gcc.c-torture/compile/pr21356.c. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133646 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22Emit trailing padding on constant vectors when TargetData says that the vectorNick Lewycky
is larger than the sum of the elements (including per-element padding). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133631 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22Replace the existing forms of ConstantArray::get() with a single formJay Foad
that takes an ArrayRef. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133615 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22Reenable the optimization added in 133415, but change the definition of a ↵Rafael Espindola
"simple" bb to be one with only one unconditional branch and no phis. Duplicating the phis in this case is possible, but requeres liveness analysis or breaking edges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133607 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21After register is spilled there should not be any DBG_VALUE referring the ↵Devang Patel
same register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21Fix some trailing issues from my introduction of MVT::untyped and its use ↵Owen Anderson
for REGISTER_SEQUENCE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133567 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21Add verbose EH table printing to SjLj exception tables.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133561 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21There could be more than one DBG_VALUE instructions for variables where all ↵Devang Patel
of them have offset based on one register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21Improve the comment printing for the EH table. This gives a much more detailedBill Wendling
explanation of what the EH table describes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133559 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21Teach dag combine to match halfword byteswap patterns.Evan Cheng
1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8) => (bswap x) >> 16 2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8)) => (rotl (bswap x) 16) This allows us to eliminate most of the def : Pat patterns for ARM rev16 revsh instructions. It catches many more cases for ARM and x86. rdar://9609108 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133503 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-20Disable again.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133446 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-20Re enable 133415 with two fixesRafael Espindola
* Don't introduce a duplicated bb in the CFG * When making a branch unconditional, clear the PredCond array so that it is really unconditional. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133432 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-20Disable the logic added by rafael in commit 133415 to see if it brings theDuncan Sands
dragonegg buildbots back to life. Original commit message: Teach early dup how to duplicate basic blocks with one successor and only phi instructions into more complex blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133430 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-20Fix PromoteIntRes_TRUNCATE: Add support for cases where theNadav Rotem
source vector type is to be split while the target vector is to be promoted. (eg: <4 x i64> -> <4 x i8> ) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-20Fix MSVC build. next() function already exists in the MSVC headers. This ↵Francois Pichet
create a overload conflict. Make sure we pick up the llvm one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133416 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-20Teach early dup how to duplicate basic blocks with one successor and only ↵Rafael Espindola
phi instructions into more complex blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-20Revamp the "ConstantStruct::get" methods. Previously, these were scatteredChris Lattner
all over the place in different styles and variants. Standardize on two preferred entrypoints: one that takes a StructType and ArrayRef, and one that takes StructType and varargs. In cases where there isn't a struct type convenient, we now add a ConstantStruct::getAnon method (whose name will make more sense after a few more patches land). It would be "really really nice" if the ConstantStruct::get and ConstantVector::get methods didn't make temporary std::vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133412 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-19Fix a FIXME by making GlobalVariable::getInitializer() return aJay Foad
const Constant *. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133400 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-19Code cleanups: Remove duplicated logic in PromotInteRes_BITCAST, reserve ↵Nadav Rotem
vector space, reuse types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133389 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-19Calls to AssertZext and getZeroExtendInReg must be made using scalar types.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133388 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-19When promoting the vector elements in CopyToParts, use vector truncNadav Rotem
instead of scalarizing, and doing an element-by-element truncat. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133382 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18fix the varargs version of StructType::get to not require an LLVMContext, ↵Chris Lattner
making usage much cleaner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133364 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18Simplify code. No change in functionality.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133350 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18Don't allocate empty read-only SmallVectors during SelectionDAG deallocation.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133348 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18Remove unused but set variables.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133347 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18Fix UMULO support for 2x register width to allow the fullEric Christopher
range without a libcall to a new mulo<mode> libcall that we'd have to create. Finishes the rest of rdar://9090077 and rdar://9210061 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133318 91177308-0d34-0410-b5e6-96231b3b80d8
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