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2011-09-13Switch extendInBlock() to take a kill slot instead of the last use slot.Jakob Stoklund Olesen
Three out of four clients prefer this interface which is consistent with extendIntervalEndTo() and LiveRangeCalc::extend(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139604 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13Use a separate LiveRangeCalc for the complement in spill modes.Jakob Stoklund Olesen
The complement interval may overlap the other intervals created, so use a separate LiveRangeCalc instance to compute its live range. A LiveRangeCalc instance can only be shared among non-overlapping intervals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139603 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13Unbreak msvc.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139581 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13Extract live range calculations from SplitKit.Jakob Stoklund Olesen
SplitKit will soon need two copies of these data structures, and the algorithms will also be useful when LiveIntervalAnalysis becomes independent of LiveVariables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139572 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12Introduce a bit of a hack.Bill Wendling
Splitting a landing pad takes considerable care because of PHIs and other nasties. The problem is that the jump table needs to jump to the landing pad block. However, the landing pad block can be jumped to only by an invoke instruction. So we clone the landingpad instruction into its own basic block, have the invoke jump to there. The landingpad instruction's basic block's successor is now the target for the jump table. But because of PHI nodes, we need to create another basic block for the jump table to jump to. This is definitely a hack, because the values for the PHI nodes may not be defined on the edge from the jump table. But that's okay, because the jump table is simply a construct to mimic what is happening in the CFG. So the values are mysteriously there, even though there is no value for the PHI from the jump table's edge (hence calling this a hack). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139545 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12Remove the -compact-regions flag.Jakob Stoklund Olesen
It has been enabled by default for a while, it was only there to allow performance comparisons. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139501 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12Add an interface for SplitKit complement spill modes.Jakob Stoklund Olesen
SplitKit always computes a complement live range to cover the places where the original live range was live, but no explicit region has been allocated. Currently, the complement live range is created to be as small as possible - it never overlaps any of the regions. This minimizes register pressure, but if the complement is going to be spilled anyway, that is not very important. The spiller will eliminate redundant spills, and hoist others by making the spill slot live range overlap some of the regions created by splitting. Stack slots are cheap. This patch adds the interface to enable spill modes in SplitKit. In spill mode, SplitKit will assume that the complement is going to spill, so it will allow it to overlap regions in order to avoid back-copies. By doing some of the spiller's work early, the complement live range becomes simpler. In some cases, it can become much simpler because no extra PHI-defs are required. This will speed up both splitting and spilling. This is only the interface to enable spill modes, no implementation yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139500 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12Update comments to reflect some (not so) recent changes.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139498 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10Fix asserts in CodeGen from:Richard Trieu
assert("error"); to: assert(0 && "error"); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139449 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09tidy up a bitChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139419 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the ↵Eli Friedman
same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Reapply r139247: Cache intermediate results during traceSiblingValue.Jakob Stoklund Olesen
In some cases such as interpreters using indirectbr, the CFG can be very complicated, and live range splitting may be forced to insert a large number of phi-defs. When that happens, traceSiblingValue can spend a lot of time zipping around in the CFG looking for defs and reloads. This patch causes more information to be cached in SibValues, and the cached values are used to terminate searches early. This speeds up spilling by 20x in one interpreter test case. For more typical code, this is just a 10% speedup of spilling. The previous version had bugs that caused miscompilations. They have been fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139378 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08Directly point debug info to the stack slot of the arugment, instead of ↵Devang Patel
trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139330 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07Revert r139247 "Cache intermediate results during traceSiblingValue."Jakob Stoklund Olesen
It broke the self host and clang-x86_64-darwin10-RA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139259 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07Cache intermediate results during traceSiblingValue.Jakob Stoklund Olesen
In some cases such as interpreters using indirectbr, the CFG can be very complicated, and live range splitting may be forced to insert a large number of phi-defs. When that happens, traceSiblingValue can spend a lot of time zipping around in the CFG looking for defs and reloads. This patch causes more information to be cached in SibValues, and the cached values are used to terminate searches early. This speeds up spilling by 20x in one interpreter test case. For more typical code, this is just a 10% speedup of spilling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139247 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= ↵James Molloy
handling to llvm-mc. Reviewed by Owen Anderson. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139237 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07Relax the MemOperands on atomics a bit. Fixes -verify-machineinstrs ↵Eli Friedman
failures for atomic laod/store on ARM. (The fix for the related failures on x86 is going to be nastier because we actually need Acquire memoperands attached to the atomic load instrs, etc.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139221 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07While sinking machine instructions, sink matching DBG_VALUEs also otherwise ↵Devang Patel
live debug variable pass will drop DBG_VALUEs on the floor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139208 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06Add codegen support for vector select (in the IR this means a selectDuncan Sands
with a vector condition); such selects become VSELECT codegen nodes. This patch also removes VSETCC codegen nodes, unifying them with SETCC nodes (codegen was actually often using SETCC for vector SETCC already). This ensures that various DAG combiner optimizations kick in for vector comparisons. Passes dragonegg bootstrap with no testsuite regressions (nightly testsuite as well as "make check-all"). Patch mostly by Nadav Rotem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06Split the init.trampoline intrinsic, which currently combines GCC'sDuncan Sands
init.trampoline and adjust.trampoline intrinsics, into two intrinsics like in GCC. While having one combined intrinsic is tempting, it is not natural because typically the trampoline initialization needs to be done in one function, and the result of adjust trampoline is needed in a different (nested) function. To get around this llvm-gcc hacks the nested function lowering code to insert an additional parent variable holding the adjust.trampoline result that can be accessed from the child function. Dragonegg doesn't have the luxury of tweaking GCC code, so it stored the result of adjust.trampoline in the memory GCC set aside for the trampoline itself (this is always available in the child function), and set up some new memory (using an alloca) to hold the trampoline. Unfortunately this breaks Go which allocates trampoline memory on the heap and wants to use it even after the parent has exited (!). Rather than doing even more hacks to get Go working, it seemed best to just use two intrinsics like in GCC. Patch mostly by Sanjoy Das. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139140 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03Fix a truly heinous bug in DAGCombine related to AssertZext.Owen Anderson
If we have a chain of zext -> assert_zext -> zext -> use, the first zext would get simplified away because of the later zext, and then the later zext would get simplified away because of the assert. The solution is to teach SimplifyDemandedBits that assert_zext demands all of the high bits of its input, rather than only those demanded by its users. No testcase because the only example I have manifests as llvm-gcc miscompiling LLVM, and I haven't found a smaller case that reproduces this problem. Fixes <rdar://problem/10063365>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Simplify by using isFullCopy().Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139019 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Darwin wants ctors/dtors to be ordered the other way round to linux.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139015 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01Revert r131152, r129796, r129761. This code is currently consideredDan Gohman
to be unreliable on platforms which require memcpy calls, and it is complicating broader legalize cleanups. It is hoped that these cleanups will make memcpy byval easier to implement in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138977 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01Don't drop alignment info on local common symbols.Benjamin Kramer
- On COFF the .lcomm directive has an alignment argument. - On ELF we fall back to .local + .comm Based on a patch by NAKAMURA Takumi. Fixes PR9337, PR9483 and PR10128. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138976 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01Permit remat of partial register defs when it is safe.Jakob Stoklund Olesen
An instruction may define part of a register where the other bits are undefined. In that case, it is safe to rematerialize the instruction. For example: %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def> The extra <imp-def> operand indicates that the instruction does not read the other parts of the virtual register, so a remat is safe. This patch simply allows multiple def operands for the virtual register. It is MI->readsVirtualRegister() that determines if we depend on a previous value so remat is impossible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01Revert r138794, "Do not try to rematerialize a value from a partial definition."Jakob Stoklund Olesen
The problem is fixed for all register allocators by r138944, so this patch is no longer necessary. <rdar://problem/10032939> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138945 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01Prevent remat of partial register redefinitions.Jakob Stoklund Olesen
An instruction that redefines only part of a larger register can never be rematerialized since the virtual register value depends on the old value in other parts of the register. This was fixed for the inline spiller in r138794. This patch fixes the problem for all register allocators, and includes a small test case. <rdar://problem/10032939> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138944 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01Teach MachineLICM reg pressure tracking code to deal with MVT::untyped. ↵Evan Cheng
Sorry, I can't come up with a small test case. rdar://10043690 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138934 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01PreRA scheduler should avoid cloning compares.Andrew Trick
Added canClobberReachingPhysRegUse() to handle a particular pattern in which a two-address instruction could be forced to interfere with EFLAGS, causing a compare to be unnecessarilly cloned. Fixes rdar://problem/5875261 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138924 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31Fix Size TypingDavid Greene
Stores sizes as uint64_t to avoid possible truncation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138901 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31Misc cleanup; addresses Duncan's comments on r138877.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138887 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31Fill in type legalization for MERGE_VALUES in all the various cases. Patch ↵Eli Friedman
by Micah Villmow. (No testcase because the issue only showed up in an out-of-tree backend.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138877 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; ↵Eli Friedman
implements 64-bit atomic load/store for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138872 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31Compress Repeated Byte OutputDavid Greene
Emit a repeated sequence of bytes using .zero. This saves an enormous amount of asm file space for certain programs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31Spelling and grammar fixes to problems found by Duncan.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138858 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30Emit segmented-stack specific code into function prologues forRafael Espindola
X86. Modify the pass added in the previous patch to call this new code. This new prologues generated will call a libgcc routine (__morestack) to allocate more stack space from the heap when required Patch by Sanjoy Das. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138812 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30Follow up to r138791.Evan Cheng
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to call a target hook to adjust the instruction. For ARM, this is used to adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC instructions have implicit def of CPSR (required since it now uses CPSR physical register dependency rather than "glue"). If the carry flag is used, then the target hook will *fill in* the optional operand with CPSR. Otherwise, the hook will remove the CPSR implicit def from the MachineInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138810 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30Do not try to rematerialize a value from a partial definition.Bob Wilson
I don't currently have a good testcase for this; will try to get one tomorrow. <rdar://problem/10032939> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138794 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29Thumb2 parsing and encoding for IT blocks.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138773 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-28Fix PR5329: pay attention to constructor/destructor priorityDuncan Sands
when outputting them. With this, the entire LLVM testsuite passes when built with dragonegg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138724 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-27These splits should be done whether they are critical edges or not.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138697 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26Update the dominator tree with the correct dominator for the new 'unwind' block.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138664 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26Split the landing pad block only if it's a critical edge. Also intelligentlyBill Wendling
split it in the other place where we're splitting critical edges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138658 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26Atomic load/store on ARM/Thumb.Eli Friedman
I don't really like the patterns, but I'm having trouble coming up with a better way to handle them. I plan on making other targets use the same legalization ARM-without-memory-barriers is using... it's not especially efficient, but if anyone cares, it's not that hard to fix for a given target if there's some better lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138621 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25Look at only the terminators of the basic block. Also, if we're using the new EHBill Wendling
scheme, return 'true' so that it doesn't try to run the old EH scheme's fixup on the new code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138605 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24Basic x86 code generation for atomic load and store instructions.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138478 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng
These are strictly utilities for registering targets and components. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24Tidy up. Trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138437 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24Add the sentinal "no handle" value to the ResumeInst.Bill Wendling
A value of -1 at a call site tells the personality function that this call isn't handled by the current function. Since the ResumeInsts are converted to calls to _Unwind_SjLj_Resume, add a (volatile) store of -1 to its 'call site'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138416 91177308-0d34-0410-b5e6-96231b3b80d8
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