aboutsummaryrefslogtreecommitdiff
path: root/lib/CodeGen
AgeCommit message (Collapse)Author
2012-02-17Revert r150288, "Allow Post-RA LICM to hoist reserved register reads."Jakob Stoklund Olesen
This caused miscompilations on out-of-tree targets, and possibly i386 as well. I'll find some other way of hoisting %rip-relative loads from loops containing calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150816 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17... and it's probably best to use the correct alignment, rather than just ↵David Chisnall
guessing that it's the same as the size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150813 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17It turns out that putting an 8-byte symbol in a 4-byte section makes Solaris ↵David Chisnall
ld sulk. GNU ld is perfectly happy with it, which is worrying for a whole other set of reasons... Thanks to Anton, Duncan and Rafael for helping me track this down. Pointy hat to Rafael for introducing the bug in the first place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150811 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17Reverse iterator - should be incrementing rather than decrementing.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150778 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17MachineScheduler shouldn't use/preserve LiveDebugVariables.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150773 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17Oops - isRegLiveIntoSuccessor is used in non-assert builds now. Remove ↵Lang Hames
NDEBUG guards. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150771 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE ↵Lang Hames
bail on reserved registers. This *should* be safe as of r150786. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150769 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17Turn off assertion, conservatively compute liveness for live-in ↵Lang Hames
un-allocatable registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150768 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16Disable machine copy propagation for now. It's known to be buggy (PR11940) ↵Benjamin Kramer
and introduces subtle miscompiles in many places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150703 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16Remove extraneous #include and spelling mistake introduced in r150669.James Molloy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150670 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16Modify the algorithm when traversing the DAGCombiner's worklist to be O(log ↵James Molloy
N) for all operations. This fixes a horrible worst case with lots of nodes where 99% of the time was being spent in std::remove. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150669 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16Oop - r150653 + r150654 broke one of my test cases. Backing out for now...Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16MachineCSE shouldn't extend the live ranges of reserved or allocatable ↵Lang Hames
registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150653 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Handle register masks in branch folding.Jakob Stoklund Olesen
Don't attempt to move instructions with regmask operands. They are most likely calls anyway. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150634 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Fix library visibility problems with VLIWPacketizer.Andrew Trick
The existing framework for postra scheduling is library local. We want to keep it that way. Soon we will have a more general MachineScheduler interface. At that time, various bits will be exposed to targets. In the meantime, the VLIWPacketizer wants to use ScheduleDAGInstrs directly, so it needs to wrapped in a PIMPL to avoid exposing it to the target interface. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150633 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Make LiveIntervals::handleMove() bundle aware.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150630 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Use 'getDataNoRel' for the section kind.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150628 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Fix assertion condition.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150627 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Modify the code that emits the module flags to use the new module flags accessorBill Wendling
method. This allows the target lowering code to not have to deal with MDNodes. Also, avoid leaking memory like a sieve by not creating a global variable for the image info section, but just emitting the code directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150624 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Don't expose DefaultVLIWSchedulerAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150619 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Remove overly conservative assert.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150608 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Generic "VLIW" packetizer based on a DFA generated from target itinerary.Andrew Trick
Patch by Sundeep! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150607 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Revert r150565 again. Appears to be a stage2 failure with dragonegg.Andrew Trick
I'll put MachineLICM back before PEI. All my arm/x86 benchmarks look good, but buildbots don't like it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150568 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Reapply r150565 with the typo fix properly merged.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150567 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15reverting r150565. Premature push.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150566 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Move PostRAMachineLICM into MachineLateOptimization. It now runs after PEI!Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150565 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Allow CodeGen (llc) command line options to work as expected.Andrew Trick
The llc command line options for enabling/disabling passes are local to CodeGen/Passes.cpp. This patch associates those options with standard pass IDs so they work regardless of how the target configures the passes. A target has two ways of overriding standard passes: 1) Redefine the pass pipeline (override TargetPassConfig::add%Stage) 2) Replace or suppress individiual passes with TargetPassConfig::substitutePass. In both cases, the command line options associated with the pass override the target default. For example, say a target wants to disable machine instruction scheduling by default: - The target calls disablePass(MachineSchedulerID) but otherwise does not override any TargetPassConfig methods. - Without any llc options, no scheduler is run. - With -enable-misched, the standard machine scheduler is run and honors the -misched=... flag to select the scheduler variant, which may be used for performance evaluation or testing. Sorry overridePass is ugly. I haven't thought of a better way without replacing the cl::opt framework. I hope to do that one day... I haven't figured out why CodeGen uses char& for pass IDs. AnalysisID is much easier to use and less bug prone. I'm using it wherever I can for internal implementation. Maybe later we can change the global pass ID definitions as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150563 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Added TargetPassConfig::disablePass/substitutePass as a general mechanism to ↵Andrew Trick
override specific passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150562 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Don't emit live ranges for physregs live-ins that are dead.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150553 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Disentangle moving a machine instr from updating LiveIntervals.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150552 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Added hook to let targets custom lower splitting of illegal vectorsPete Cooper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150550 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Fix global live range splitting regmask accuracy.Jakob Stoklund Olesen
Pretend that regmask interference ends at the 'dead' slot, even when there is other interference ending at the 'reg' slot of the same instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150531 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Fix details in local live range splitting with regmasks.Jakob Stoklund Olesen
Perform all comparisons at instruction granularity, and make sure register masks on uses count in both gaps. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150530 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Handle regmasks in findRegisterDefOperandIdx().Jakob Stoklund Olesen
Only accept register masks when looking for an 'overlapping' def. When Overlap is not set, the function searches for a proper definition of Reg. This means MI->modifiesRegister() considers register masks, but MI->definesRegister() doesn't. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150529 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Use the proper clobber check in handleLiveInRegister().Jakob Stoklund Olesen
When a physreg is live in to a basic block, look for any instruction in the block that clobbers the physreg. The instruction doesn't have to properly redefine the register, any overlapping clobber is OK. This slightly changes live ranges when compiling with register masks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150528 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Dump live intervals in numerical order.Jakob Stoklund Olesen
The old DenseMap hashed order was very confusing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150527 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Don't create a new copy of reserved regs - we already have one handy.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150525 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Add code to the target lowering object file module to handle module flags.Bill Wendling
The MachO back-end needs to emit the garbage collection flags specified in the module flags. This is a WIP, so the front-end hasn't been modified to emit these flags just yet. Documentation and front-end switching to occur soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150507 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Update MachineVerifier to check the new physreg live-in rules.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150496 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Tighten physical register invariants: Allocatable physical registers canLang Hames
only be live in to a block if it is the function entry point or a landing pad. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150494 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Fix PR12000. Some vector operations may use scalar operands with typesNadav Rotem
that are greater than the vector element type. For example BUILD_VECTOR of type <1 x i1> with a constant i8 operand. This patch fixes the assertion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150477 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Turn push_back loops into append/insert.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150471 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Rename getExceptionAddressRegister() to getExceptionPointerRegister() for ↵Lang Hames
consistency with setExceptionPointerRegister(...). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Use convenience function for consistency.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150457 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Don't reserve the R0 and R1 registers here. We don't use these registers, andBill Wendling
marking them as "live-in" into a BB ruins some invariants that the back-end tries to maintain. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150437 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Don't recalculate the size of the vector each time through the loop.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150436 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Add register mask support to ScheduleDAGRRList.Jakob Stoklund Olesen
The scheduler will sometimes check the implicit-def list on instructions to properly handle pre-colored DAG edges. Also check any register mask operands for physreg clobbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150428 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13LiveIntervalAnalysis does not depend on MachineLoopInfo.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150411 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Check regmask interference for -join-physregs.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150404 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Fix a bug in DAGCombine for the optimization of BUILD_VECTOR. We cant ↵Nadav Rotem
generate a shuffle node from two vectors of different types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150383 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-07-08 12:44:51 +0000