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2012-05-18Refactor data-in-code annotations.Jim Grosbach
Use a dedicated MachO load command to annotate data-in-code regions. This is the same format the linker produces for final executable images, allowing consistency of representation and use of introspection tools for both object and executable files. Data-in-code regions are annotated via ".data_region"/".end_data_region" directive pairs, with an optional region type. data_region_directive := ".data_region" { region_type } region_type := "jt8" | "jt16" | "jt32" | "jta32" end_data_region_directive := ".end_data_region" The previous handling of ARM-style "$d.*" labels was broken and has been removed. Specifically, it didn't handle ARM vs. Thumb mode when marking the end of the section. rdar://11459456 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157062 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-18Remove duplicate code that we could just fallthrough to.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157060 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-18Simplify RegisterCoalescer::copyCoalesceInMBB().Jakob Stoklund Olesen
It is no longer necessary to separate VirtCopies, PhysCopies, and ImpDefCopies. Implicitly defined copies are extremely rare after we added the ProcessImplicitDefs pass, and physical register copies are not joined any longer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157059 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-18Remove support for PhysReg joining.Jakob Stoklund Olesen
This has been disabled for a while, and it is not a feature we want to support. Copies between physical and virtual registers are eliminated by good hinting support in the register allocator. Joining virtual and physical registers is really a form of register allocation, and the coalescer is not properly equipped to do that. In particular, it cannot backtrack coalescing decisions, and sometimes that would cause it to create programs that were impossible to register allocate, by exhausting a small register class. It was also very difficult to keep track of the live ranges of aliasing registers when extending the live range of a physreg. By disabling physreg joining, we can let fixed physreg live ranges remain constant throughout the register allocator super-pass. One type of physreg joining remains: A virtual register that has a single value which is a copy of a reserved register can be merged into the reserved physreg. This always lowers register pressure, and since we don't compute live ranges for reserved registers, there are no problems with aliases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157055 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-18Recommited reworked r156804:Stepan Dyatkovskiy
SelectionDAGBuilder::Clusterify : main functinality was replaced with CRSBuilder::optimize, so big part of Clusterify's code was reduced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157046 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-18Teach two-address pass to update the "source" map so it doesn't perform aEvan Cheng
non-profitable commute using outdated info. The test case would still fail because of poor pre-RA schedule. That will be fixed by MI scheduler. rdar://11472010 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157038 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17commentsAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157020 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17misched: trace ReadyQ.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157007 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17misched: Added 3-level regpressure back-off.Andrew Trick
Introduce the basic strategy for register pressure scheduling. 1) Respect target limits at all times. 2) Indentify critical register classes (pressure sets). Track pressure within the scheduled region. Avoid increasing scheduled pressure for critical registers. 3) Avoid exceeding the max pressure of the region prior to scheduling. Added logic for picking between the top and bottom ready Q's based on regpressure heuristics. Status: functional but needs to be asjusted to achieve good results. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157006 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17commentAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157005 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17regpressure: Fix getMaxUpwardPressureDelta.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157004 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17misched: fix liveness iteratorsAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157003 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157002 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17Never clear <undef> flags on already joined copies.Jakob Stoklund Olesen
RegisterCoalescer set <undef> flags on all operands of copy instructions that are scheduled to be removed. This is so they won't affect shrinkToUses() by introducing false register reads. Make sure those <undef> flags are never cleared, or shrinkToUses() could cause live intervals to end at instructions about to be deleted. This would be a lot simpler if RegisterCoalescer could just erase joined copies immediately instead of keeping all the to-be-deleted instructions around. This fixes PR12862. Unfortunately, bugpoint can't create a sane test case for this. Like many other coalescer problems, this failure depends of a very fragile series of events. <rdar://problem/11474428> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17Fix a verifier bug.Jakob Stoklund Olesen
Make sure useless (def-only) intervals also get verified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157000 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17Relax the requirement that the exception object must be an instruction. DuringBill Wendling
bugpoint-ing, it may turn into something else. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156998 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17SelectionDAGBuilder: CaseBlock, CaseRanges and CaseCmp changed ↵Stepan Dyatkovskiy
representation of Low and High from signed to unsigned. Since unsigned ints usually simpler, faster and allows to reduce some extra signed bit checks needed before <,>,<=,>= comparisons. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156985 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-16Set sub-register <undef> flags more accurately.Jakob Stoklund Olesen
When widening an existing <def,reads-undef> operand to a super-register, it may be necessary to clear the <undef> flag because the wider register is now read-modify-write through the instruction. Conversely, it may be necessary to add an <undef> flag when the coalescer turns a full-register def into a sub-register def, but the larger register wasn't live before the instruction. This happens in test/CodeGen/ARM/coalesce-subregs.ll, but the test is too small for the <undef> flags to affect the generated code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156951 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-16Fix a thinko in DisintegrateMERGE_VALUES. Patch by Xiaoyi Guo.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156909 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Enable sub-sub-register copy coalescing.Jakob Stoklund Olesen
It is now possible to coalesce weird skewed sub-register copies by picking a super-register class larger than both original registers. The included test case produces code like this: vld2.32 {d16, d17, d18, d19}, [r0]! vst2.32 {d18, d19, d20, d21}, [r0] We still perform interference checking as if it were a normal full copy join, so this is still quite conservative. In particular, the f1 and f2 functions in the included test case still have remaining copies because of false interference. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156878 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Teach RegisterCoalescer to handle symmetric sub-register copies.Jakob Stoklund Olesen
It is possible to coalesce two overlapping registers to a common super-register that it larger than both of the original registers. The important difference is that it may be necessary to rewrite DstReg operands as well as SrcReg operands because the sub-register index has changed. This behavior is still disabled by CoalescerPair. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156869 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Handle NewReg==OldReg in renameRegister().Jakob Stoklund Olesen
This can happen when widening a virtual register to a super-register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156867 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15We never call adjustCopiesBackFrom() for partial copies.Jakob Stoklund Olesen
There is no need to look at an always null SrcIdx. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156866 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Extend the CoalescerPair interface to handle symmetric sub-register copies.Jakob Stoklund Olesen
Now both SrcReg and DstReg can be sub-registers of the final coalesced register. CoalescerPair::setRegisters still rejects such copies because RegisterCoalescer doesn't yet handle them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156848 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Add -enable-aa-sched-mi, off by default, for AliasAnalysis inside ↵Andrew Trick
MachineScheduler. This feature avoids creating edges in the scheduler's dependence graph for non-aliasing memory operations according to whichever alias analysis is available. It has been fully tested in Hexagon. Before making this default, it needs to be extended to handle multiple MachineMemOperands, compile time needs more evaluation, and benchmarking on X86 and ARM is needed. Patch by Sergei Larin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156842 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Allow MCCodeEmitter access to the target MCRegisterInfo.Jim Grosbach
Add the MCRegisterInfo to the factories and constructors. Patch by Tom Stellard <Tom.Stellard@amd.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156828 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Rejected r156804 due to buildbots failures.Stepan Dyatkovskiy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156808 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15SelectionDAGBuilder::Clusterify : main functinality was replaced with ↵Stepan Dyatkovskiy
CRSBuilder::optimize, so big part of Clusterify's code was reduced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156804 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Don't access MO reference after invalidating operand list.Jakob Stoklund Olesen
This should unbreak llvm-x86_64-linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156778 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Fix PR12821.Jakob Stoklund Olesen
RAFast must add an <imp-def> operand when it is rewriting a sub-register def that isn't a read-modify-write. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156777 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Rename @llvm.debugger to @llvm.debugtrap.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156774 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-12Don't look for empty live ranges in the unions.Jakob Stoklund Olesen
Empty live ranges represent undef and still get allocated, but they won't appear in LiveIntervalUnions. Patch by Patrik Hägglund! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156685 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Revert 156658.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156662 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11[fast-isel] Fast-isel doesn't use the expect intrinsic.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156658 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11ARM: peephole optimization to remove cmp instructionManman Ren
This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156599 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),Dan Gohman
but it generates int3 on x86 instead of ud2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156593 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10misched: Print machineinstrs with -debug-only=mischedAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156576 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10misched: tracing register pressure heuristics.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156575 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10misched: Add register pressure backoff to ConvergingScheduler.Andrew Trick
Prioritize the instruction that comes closest to keeping pressure under the target's limit. Then prioritize instructions that avoid increasing the max pressure in the scheduled region. The max pressure heuristic is a tad aggressive. Later I'll fix it to consider the unscheduled pressure as well. WIP: This is mostly functional but untested and not likely to do much good yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156574 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10misched: Release only unscheduled nodes into ReadyQ.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156573 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10misched: Added ReadyQ container wrapper for Top and Bottom Queues.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156572 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10misched: Introducing Top and Bottom register pressure trackers during ↵Andrew Trick
scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156571 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10RegPressure: API for speculatively checking instruction pressure.Andrew Trick
Added getMaxExcessUpward/DownwardPressure. They somewhat abuse the tracker by speculatively handling an instruction out of order. But it is convenient for now. In the future, we will cache each instruction's pressure contribution to make this efficient. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156561 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10RegPressure: fix array index iteration style.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156560 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Revert: 156550 "ARM: peephole optimization to remove cmp instruction"Manman Ren
This commit broke an external linux bot and gave a compile-time warning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10ARM: peephole optimization to remove cmp instructionManman Ren
This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156550 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-08Fix thinko in conditional.Eric Christopher
Part of rdar://11352000 and should bring the buildbots back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156421 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-08DAGCombiner should not change the type of an extract_vector index.Jim Grosbach
When a combine twiddles an extract_vector, care should be take to preserve the type of the index operand. No luck extracting a reasonable testcase, unfortunately. rdar://11391009 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156419 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-08Formatting fixes.Akira Hatanaka
Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156409 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-08Handle OpDeref in case it comes in as a register operand.Eric Christopher
Part of rdar://11352000 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156405 91177308-0d34-0410-b5e6-96231b3b80d8
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