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2012-07-09indentationAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159958 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Teach the DAG combiner to turn sitofp/uitofp from i1 into a conditional ↵Owen Anderson
move, since there are only two possible values. Previously, this would become an integer extension operation, followed by a real integer->float conversion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159957 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09LOCALMODs from hg 0b098ca44de7 against r158408 (hg 90a87d6bfe45)Derek Schuff
(only non-new files; new files in git 4f429c8b) Change-Id: Ia39f818088485bd90e4d048db404f8d6ba5f836b
2012-07-07I'm introducing a new machine model to simultaneously allow simpleAndrew Trick
subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06Whitespace.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159839 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06[fast-isel] Tell fast-isel to do nothing with the new donothing intrinsic.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159837 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06Fix PR13202 and a regtest.Alexey Samsonov
DwarfDebug class could generate the same (inlined) DIVariable twice: 1) when trying to find abstract debug variable for a concrete inlined instance. 2) when explicitly collecting info for variables that were optimized out. This change makes sure that this duplication won't happen and makes Clang pass "gdb.opt/inline-locals" test from gdb testsuite. Reviewed by Eric Christopher. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159811 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06Add some comments suggested in code review.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159800 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-05Optimize extendIntervalEndTo a tiny bit by saving one call through theChandler Carruth
vector erase. No functionality changed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159746 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-05Finish fixing the MachineOperand hashing, providing a nice modernChandler Carruth
hash_value overload for MachineOperands. This addresses a FIXME sufficient for me to remove it, and cleans up the code nicely too. The important changes to the hashing logic: - TargetFlags are now included in all of the hashes. These were complete missed. - Register operands have their subregisters and whether they are a def included in the hash. - We now actually hash all of the operand types. Previously, many operand types were simply *dropped on the floor*. For example: - Floating point immediates - Large integer immediates (>64-bit) - External globals! - Register masks - Metadata operands - It removes the offset from the block-address hash; I'm a bit suspicious of this, but isIdenticalTo doesn't consider the offset for black addresses. Any patterns involving these entities could have triggered extreme slowdowns in MachineCSE or PHIElimination. Let me know if there are PRs you think might be closed now... I'm looking myself, but I may miss them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159743 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-05All cases are covered, no need for a default. This deals with theDuncan Sands
corresponding clang warning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159742 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-05The hash function for MI expressions, used by MachineCSE, is reallyChandler Carruth
broken. This patch fixes the superficial problems which lead to the intractably slow compile times reported in PR13225. The specific issue is that we were failing to include the *offset* of a global variable in the hash code. Oops. This would in turn cause all MIs which were only distinguishable due to operating on different offsets of a global variable to produce identical hash functions. In some of the test cases attached to the PR I saw hash table activity where there were O(1000) probes-per-lookup *on average*. A very few entries were responsible for most of these probes. There is still quite a bit more to do here. The ad-hoc layering of data in MachineOperands makes them *extremely* brittle to hash correctly. We're missing quite a few other cases, the only ones I've fixed here are the specific MO types which were allowed through the assert() in getOffset(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159741 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-05Use the right kind of booleans: we were emitting 0/1 booleans, instead of 0/-1Duncan Sands
booleans. Patch by James Benton. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159739 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-05Remove ParentMap. You can just ask the domnode for its parent. No functionalityNick Lewycky
change. Move the "Not profitable, avoid CSE!" debug message next to where we fail the check for profitability and use a different message for avoiding CSE due to being in different register classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159729 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04Allow trailing physreg RegisterSDNode operands on non-variadic instructions.Jakob Stoklund Olesen
Also allow trailing register mask operands on non-variadic both MachineSDNodes and MachineInstrs. The extra physreg RegisterSDNode operands are added to the MI as <imp-use> operands. This makes it possible to have non-variadic call instructions. Call and return instructions really are non-variadic, the argument registers should only be used implicitly - they are not part of the encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159727 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04Print SlotIndexes when available for -print-machineinstrs.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159726 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04Allow multiple terminators to read virtual registers.Jakob Stoklund Olesen
Find the kill as the last terminator to read SrcReg. Patch by Philipp Brüschweiler! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159722 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04Make sure -print-machineinstrs applies to the first pass as well.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159720 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04Reverted r156659, due to probable performance regressions, DenseMap should ↵Stepan Dyatkovskiy
be used here: IntegersSubsetMapping - Replaced type of Items field from std::list with std::map. In neares future I'll test it with DenseMap and do the correspond replacement if possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159703 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04Reduce some code duplication.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159701 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04Fix some ascii art in a comment to not have trailing backslashes (inspirationMatt Beaumont-Gay
from IfConversion.cc), and fix some spelling and grammar in the surrounding prose. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159699 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04Add an experimental early if-conversion pass, off by default.Jakob Stoklund Olesen
This pass performs if-conversion on SSA form machine code by speculatively executing both sides of the branch and using a cmov instruction to select the result. This can help lower the number of branch mispredictions on architectures like x86 that don't have predicable instructions. The current implementation is very aggressive, and causes regressions on mosts tests. It needs good heuristics that have yet to be implemented. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159694 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-03Part of r159527. Splitted into series of patches and gone with fixed PR13256:Stepan Dyatkovskiy
IntegersSubsetMapping - Replaced type of Items field from std::list with std::map. In neares future I'll test it with DenseMap and do the correspond replacement if possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159659 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Revert "IntRange:" as it appears to be breaking self hosting.Eric Christopher
This reverts commit b2833d9dcba88c6f0520cad760619200adc0442c. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159618 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02All glory to address sanitizer. ;]Chandler Carruth
It appears to have caught a use-after-free introduced as by r159567 and/or friends which call 'addPass' from many more places. The bug in 'addPass' doesn't appear to be new, and was spotted by inspection when ASan shown a bright light of a stacktrace at these functions. Hopefully this will fix the ASan failure -- I have no test case other than running an ASan-built clang over the test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159614 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Target option DisableJumpTables is a gross hack. Move it to TargetLowering ↵Evan Cheng
instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159611 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02misched: allow NULL InstrItineraries.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159599 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Turn an assert into an error to make it a bit more friendly.Eric Christopher
Part of rdar://6880388 and rdar://11766377 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159590 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Extend TargetPassConfig to allow running only a subset of the normal passes.Bob Wilson
This is still a work in progress but I believe it is currently good enough to fix PR13122 "Need unit test driver for codegen IR passes". For example, you can run llc with -stop-after=loop-reduce to have it dump out the IR after running LSR. Serializing machine-level IR is not yet supported but we have some patches in progress for that. The plan is to serialize the IR to a YAML file, containing separate sections for the LLVM IR, machine-level IR, and whatever other info is needed. Chad suggested that we stash the stop-after pass in the YAML file and use that instead of the start-after option to figure out where to restart the compilation. I think that's a great idea, but since it's not implemented yet I put the -start-after option into this patch for testing purposes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159570 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Move assertion with TargetPassConfig's Initialized flag.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159569 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Consistently use AnalysisID types in TargetPassConfig.Bob Wilson
This makes it possible to just use a zero value to represent "no pass", so the phony NoPassID global variable is no longer needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159568 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Add all codegen passes to the PassManager via TargetPassConfig.Bob Wilson
This is a preliminary step toward having TargetPassConfig be able to start and stop the compilation at specified passes for unit testing and debugging. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159567 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Added assertion in getVRegDef of MachineRegisterInfo to make sure the virtualManman Ren
register does not have multiple definitions. Modified TwoAddressInstructionPass to use getUniqueVRegDef instead of getVRegDef. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159545 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick
Reapplies r159406 with minor cleanup. The regressions appear to have been spurious. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159541 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02IntRange:Stepan Dyatkovskiy
- Changed isSingleNumber method behaviour. Now this flag is calculated on demand. IntegersSubsetMapping - Optimized diff operation. - Replaced type of Items field from std::list with std::map. - Added new methods: bool isOverlapped(self &RHS) void add(self& RHS, SuccessorClass *S) void detachCase(self& NewMapping, SuccessorClass *Succ) void removeCase(SuccessorClass *Succ) SuccessorClass *findSuccessor(const IntTy& Val) const IntTy* getCaseSingleNumber(SuccessorClass *Succ) IntegersSubsetTest - DiffTest: Added checks for successors. SimplifyCFG Updated SwitchInst usage (now it is case-ragnes compatible) for - SimplifyEqualityComparisonWithOnlyPredecessor - FoldValueComparisonIntoPredecessors git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159527 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-01Now that RegistersDefinedFromSameValue handles one instruction being anRafael Espindola
implicit_def, the other instruction can be anything, including instructions that define multiple values. Be careful about that and don't assume what operand 0 is. Fixes pr13249. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159509 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-30Handle implicit_defs in the register coalescer. I am still trying to produceRafael Espindola
a reduced testcase, but this fixes pr13209. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159479 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29Add SrcReg2 to analyzeCompare and optimizeCompareInstr to handle CompareManman Ren
instructions with two register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159465 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29Clear kill flags in InstrEmitter::EmitSubregNode().Jakob Stoklund Olesen
When a local virtual register is made global, make sure to clear any existing kill flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159461 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29Check for extra kill flags on live-out virtual registers.Jakob Stoklund Olesen
This would previously get reported as the misleading "Virtual register def doesn't dominate all uses." git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29Add getUniqueVRegDef to MachineRegisterInfo.Manman Ren
This comes in handy during peephole optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159453 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29Cleanup in DwarfDebug - fix a typo and remove two unused functionsAlexey Samsonov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159433 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29Move llvm/Support/IRBuilder.h -> llvm/IRBuilder.hChandler Carruth
This was always part of the VMCore library out of necessity -- it deals entirely in the IR. The .cpp file in fact was already part of the VMCore library. This is just a mechanical move. I've tried to go through and re-apply the coding standard's preferred header sort, but at 40-ish files, I may have gotten some wrong. Please let me know if so. I'll be committing the corresponding updates to Clang and Polly, and Duncan has DragonEgg. Thanks to Bill and Eric for giving the green light for this bit of cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159421 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29The DIBuilder class is just a wrapper around debug info creationBill Wendling
(a.k.a. MDNodes). The module doesn't belong in Analysis. Move it to the VMCore instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159414 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick
This reverts commit r159406. I noticed a performance regression so I'll back out for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159411 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29misched: avoid scheduling instructions that can't be dispatched.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159408 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29misched: count micro-ops toward the issue limit.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159407 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29Make NumMicroOps a variable in the subtarget's instruction itinerary.Andrew Trick
The TargetInstrInfo::getNumMicroOps API does not change, but soon it will be used by MachineScheduler. Now each subtarget can specify the number of micro-ops per itinerary class. For ARM, this is currently always dynamic (-1), because it is used for load/store multiple which depends on the number of register operands. Zero is now a valid number of micro-ops. This can be used for nop pseudo-instructions or instructions that the hardware can squash during dispatch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159406 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-28add a new @llvm.donothing intrinsic that, well, does nothing, and teach ↵Nuno Lopes
CodeGen to ignore calls to it git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159383 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-28'Promote' vector [su]int_to_fp should widen elements.Jim Grosbach
Teach vector legalization how to honor Promote for int to float conversions. The code checking whether to promote the operation knew to look at the operand, but the actual promotion code didn't. This fixes that. The operand is promoted up via [zs]ext. rdar://11762659 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159378 91177308-0d34-0410-b5e6-96231b3b80d8
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