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Soon, RegAllocGreedy will start splitting live ranges, and then deferred
spilling won't work anyway.
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The spiller should only spill. The register allocator will drive live range
splitting, it has the needed information about register pressure and
interferences.
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interference check.
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registers for a given virtual register.
Reserved registers are filtered from the allocation order, and any valid hint is
returned as the first suggestion.
For target dependent hints, a number of arcane target hooks are invoked.
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f:
.cfi_startproc
nop
.cfi_endproc
assembled (on ELF).
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Necessary for byval support on ARM. Radar 7662569.
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heuristic to reshuffle register assignments when we can't find an
available reg.
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references instead.
Similarly, IntervalMap::begin() is almost as expensive as find(), so use find(x)
instead of begin().advanceTo(x);
This makes RegAllocBasic run another 5% faster.
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instead.
This fixes radar 8730409.
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The hint is simply tried first and then forgotten if it couldn't be allocated
immediately.
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abstract priority queue interface in subclasses that want to override the
priority calculations.
Subclasses must provide a getPriority() implementation instead.
This approach requires less code as long as priorities are expressable as simple
floats, and it avoids the dangers of defining potentially expensive priority
comparison functions.
It also should speed up priority_queue operations since they no longer have to
chase pointers when comparing registers. This is not measurable, though.
Preferably, we shouldn't use floats to guide code generation. The use of floats
here is derived from the use of floats for spill weights. Spill weights have a
dynamic range that doesn't lend itself easily to a fixpoint implementation.
When someone invents a stable spill weight representation, it can be reused for
allocation priorities.
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both forward and backward scheduling. Rename it to
ScoreboardHazardRecognizer (Scoreboard is one word). Remove integer
division from the scoreboard's critical path.
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This new register allocator is initially identical to RegAllocBasic, but it will
receive all of the tricks that RegAllocBasic won't get.
RegAllocGreedy will eventually replace linear scan.
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Minor optimization to the use of IntervalMap iterators. They are fairly
heavyweight, so prefer SI.valid() over SI != end().
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This speeds up RegAllocBasic by 20%, not counting releaseMemory which becomes
way faster.
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zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method
trunc(), to be const and to return a new value instead of modifying the
object in place.
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This will be used to truncate live range of DBG_VALUE instruction by register allocator and friends.
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message instead of creating DBG_VALUE for undefined value in reg0.
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as llc + llvm-mc. This time ELF is not changed and I tested that llvm-gcc
bootstrap on darwin10 using darwin9's assembler and linker.
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linux and darwin assemblers happy :-(
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that no relocations are used (on MochO).
Fixes llc producing different output from llc + llvm-mc.
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StrongPHIElimination.
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PHIElimination.h.
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time, this method existed, but now PHIElimination uses the method of the same
name on MachineBasicBlock.
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function so that it can be shared with StrongPHIElimination.
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be emitted.
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The StrongPHIElimination pass did not work, and nobody has worked on it for two
years.
A rewrite is underway, so I am leaving this shell pass instead of deleting it
completely.
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Scan the MachineFunction for DBG_VALUE instructions, and replace them with a
data structure similar to LiveIntervals. The live range of a DBG_VALUE is
determined by propagating it down the dominator tree until a new DBG_VALUE is
found. When a DBG_VALUE lives in a register, its live range is confined to the
live range of the register's value.
LiveDebugVariables runs before coalescing, so DBG_VALUEs are not artificially
extended when registers are joined.
The missing half will recreate DBG_VALUE instructions from the intervals when
register allocation is complete.
The pass is disabled by default. It can be enabled with the temporary command
line option -live-debug-variables.
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setAllBits(), setBit(unsigned), etc.
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legalization time. Since at legalization time there is no mapping from
SDNode back to the corresponding LLVM instruction and the return
SDNode is target specific, this requires a target hook to check for
eligibility. Only x86 and ARM support this form of sibcall optimization
right now.
rdar://8707777
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