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Thanks, Duncan.
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the LowerPartSet(). It didn't handle the situation correctly when
the low, high argument values are in reverse order (low > high)
with 'Val' type i32 (a corner case).
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APIs emitting constants now take an additional parameter signifying the address space in which to emit. The APIs like getData8BitsDirective() etc are made virtual enabling targets to be able to define appropirate directivers for various sizes and address spaces.
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If a MachineInstr doesn't have a memoperand but has an opcode that
is known to load or store, assume its memory reference may alias
*anything*, including stack slots which the compiler completely
controls.
To partially compensate for this, teach the ScheduleDAG building
code to do basic getUnderlyingValue analysis. This greatly
reduces the number of instructions that require restrictive
dependencies. This code will need to be revisited when we start
doing real alias analysis, but it should suffice for now.
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- Modify ReassociateOps so that the resulting SDValue is what the comment claims
it is.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63365 91177308-0d34-0410-b5e6-96231b3b80d8
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don't try to insert loads/stores between call frame setup and the actual call.
This fixes the last known failure for the pre-alloc-splitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63339 91177308-0d34-0410-b5e6-96231b3b80d8
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BUILD_VECTOR and conversions to stack operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63333 91177308-0d34-0410-b5e6-96231b3b80d8
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some assertions.
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basic blocks have live-ins.
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the element indices may be equal if either one is not a
constant.
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change.
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and an iterator invalidation issue.
FreeBench/pifft no longer miscompiles with these fixes!
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vast majority of code size regressions introduced by pre-alloc-splitting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63274 91177308-0d34-0410-b5e6-96231b3b80d8
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- Modify TableGen to add the DebugLoc when calling getTargetNode.
(The light-weight wrappers are only temporary. The non-DebugLoc version will be
removed once the whole debug info stuff is finished with.)
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dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.
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register getReg() should not call getFreeReg().
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functions. Currently omitted: memcpy, memmove, memset.
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classes (those that reasonably have a DebugLoc
associated with them).
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widened.
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new isOperationLegalOrCustom, which does what isOperationLegal
previously did.
Update a bunch of callers to use isOperationLegalOrCustom
instead of isOperationLegal. In some case it wasn't obvious
which behavior is desired; when in doubt I changed then to
isOperationLegalOrCustom as that preserves their previous
behavior.
This is for the second half of PR3376.
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shift amounts, to avoid implicitly assuming that
target architectures will ignore the high bits.
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a uint64_t to verify that the value is in range for the given type,
to help catch accidental overflow. Fix a few places that relied on
getConstant implicitly truncating the value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63128 91177308-0d34-0410-b5e6-96231b3b80d8
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