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2011-02-03Defer SplitKit value mapping until all defs are available.Jakob Stoklund Olesen
The greedy register allocator revealed some problems with the value mapping in SplitKit. We would sometimes start mapping values before all defs were known, and that could change a value from a simple 1-1 mapping to a multi-def mapping that requires ssa update. The new approach collects all defs and register assignments first without filling in any live intervals. Only when finish() is called, do we compute liveness and mapped values. At this time we know with certainty which values map to multiple values in a split range. This also has the advantage that we can compute live ranges based on the remaining uses after rematerializing at split points. The current implementation has many opportunities for compile time optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124765 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-02Add support to describe template value parameter in debug info.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124755 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-02Add support to describe template parameter type in debug info.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124752 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-02Given a pair of floating point load and store, if there are no other uses ofEvan Cheng
the load, then it may be legal to transform the load and store to integer load and store of the same width. This is done if the target specified the transformation as profitable. e.g. On arm, this can transform: vldr.32 s0, [] vstr.32 s0, [] to ldr r12, [] str r12, [] rdar://8944252 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124708 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-01Take Bill Wendling's suggestion for structuring a couple of asserts.Matt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124688 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-31Keep track of incoming argument's location while emitting LiveIns.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124611 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-31Fix bug where ReduceLoadWidth was creating illegal ZEXTLOAD instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124587 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-30Clarify the LSDASection NULL checkAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-30Respect the -tail-dup-size command line option even when optimizing for size.Jakob Stoklund Olesen
This is similar to the -unroll-threshold option. There should be no change in behavior when -tail-dup-size is not explicit on the llc command line. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124564 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-30Teach DAGCombine to fold fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, ↵Benjamin Kramer
c1+c2) when c1 equals the amount of bits that are truncated off. This happens all the time when a smul is promoted to a larger type. On x86-64 we now compile "int test(int x) { return x/10; }" into movslq %edi, %rax imulq $1717986919, %rax, %rax movq %rax, %rcx shrq $63, %rcx sarq $34, %rax <- used to be "shrq $32, %rax; sarl $2, %eax" addl %ecx, %eax This fires 96 times in gcc.c on x86-64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124559 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-29Add the missing sub identity "A-(A-B) -> B" to DAGCombine.Benjamin Kramer
This happens e.g. for code like "X - X%10" where we lower the modulo operation to a series of multiplies and shifts that are then subtracted from X, leading to this missed optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124532 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-29Re-apply r124518 with fix. Watch out for invalidated iterator.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124526 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-29Revert r124518. It broke Linux self-host.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124522 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-29Re-commit r124462 with fixes. Tail recursion elim will now dup ret into ↵Evan Cheng
unconditional predecessor to enable TCE on demand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-28Revert r124462. There are a few big regressions that I need to fix first.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124478 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-28Fix build with stdcxx by using llvm::next. Patch by Joerg Sonnenberger!Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124472 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-28Print the visibility of declarations.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124468 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-28- Stop simplifycfg from duplicating "ret" instructions into unconditionalEvan Cheng
branches. PR8575, rdar://5134905, rdar://8911460. - Allow codegen tail duplication to dup small return blocks after register allocation is done. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124462 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27Remove a temporary workaround for a lencod miscompile. Depends on the fix in ↵Andrew Trick
r124442. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124443 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27VirtRegRewriter fix: update kill flags, which are used by the scavenger.Andrew Trick
rdar://problem/8893967: JM/lencod miscompile at -arch armv7 -mthumb -O3 Added ResurrectKill to remove kill flags after we decide to reused a physical register. And (hopefully) ensure that we call it in all the right places. Sorry, I'm not checking in a unit test given that it's a miscompile I can't reproduce easily with a toy example. Failures in the rewriter depend on a series of heuristic decisions maked during one of the many upstream phases in codegen. This case would require coercing regalloc to generate a couple of rematerialzations in a way that causes the scavenger to reuse the same register at just the wrong point. The general way to test this is to implement kill flags verification. Then we could have a simple, robust compile-only unit test. That would be worth doing if the whole pass was not about to disappear. At this point we focus verification work on the next generation of regalloc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124442 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27Speculatively revert r124380.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124397 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27While legalizing SDValues do not drop SDDbgValues, trasfer them to new legal ↵Devang Patel
nodes. Take 2. This includes fix for dragonegg crash. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124380 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27Avoid modifying the OneClassForEachPhysReg map while iterating over it.Bob Wilson
Linear scan regalloc is currently assuming that any register aliased with a member of a regclass must also be in at least one regclass. That is not always true. For example, for X86, RIP is in a regclass but IP is not. If you're unlucky, this can cause a crash by invalidating the iterator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124365 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27Try harder to not have unused variables.Matt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124350 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27Opt-mode -Wunused-variable cleanupMatt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124346 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27Reapply 124301Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26Initialize variable to get rid of clang warning.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124331 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26Revert 124301.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124327 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26Revert r124302Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26[AVX] Add INSERT_SUBVECTOR and support it on x86. This provides aDavid Greene
default implementation for x86, going through the stack in a similr fashion to how the codegen implements BUILD_VECTOR. Eventually this will get matched to VINSERTF128 if AVX is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124307 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26While legalizing SDValues do not drop SDDbgValues, trasfer them to new legal ↵Devang Patel
nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124302 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26Process valid SDDbgValues even if the node does not have any order assigned.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124301 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26Refactor.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124300 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26[AVX] Support EXTRACT_SUBVECTOR on x86. This provides a defaultDavid Greene
implementation of EXTRACT_SUBVECTOR for x86, going through the stack in a similr fashion to how the codegen implements BUILD_VECTOR. Eventually this will get matched to VEXTRACTF128 if AVX is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124292 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26Rename member variables to follow the rest of LLVM.Jakob Stoklund Olesen
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124257 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-25Provide an interface to transfer SDDbgValue from one SDNode to another.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-25Resolve DanglingDbgValue of PHI nodes where the use follows dbg.value ↵Devang Patel
intrinisic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124203 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-25This assertion is too restrictive, it does not apply for dangling dbg value ↵Devang Patel
nodes (nodes where dbg.value intrinsic preceds use of the value). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124202 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-24Support printing exception section into the current one. This is the case ↵Anton Korobeynikov
when LSDASection is blank git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124150 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-24Speculatively revert r124138.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124142 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-24Resolve DanglingDbgValue of PHI nodes where the use follows dbg.value ↵Devang Patel
intrinisic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124138 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-24Temporarily workaround JM/lencod miscompile (SIGSEGV).Andrew Trick
rdar://problem/8893967 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124137 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23Add support for the --noexecstack option.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124077 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23Null initialize a few variables flagged byTed Kremenek
clang's -Wuninitialized-experimental warning. While these don't look like real bugs, clang's -Wuninitialized-experimental analysis is stricter than GCC's, and these fixes have the benefit of being general nice cleanups. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124073 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23Delay the creation of eh_frame so that the user can change the defaults.Rafael Espindola
Add support for SHT_X86_64_UNWIND. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23Remove more duplicated code.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124056 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23Remove duplicated code.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124054 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Enable support for precise scheduling of the instruction selectionAndrew Trick
DAG. Disable using "-disable-sched-cycles". For ARM, this enables a framework for modeling the cpu pipeline and counting stalls. It also activates several heuristics to drive scheduling based on the model. Scheduling is inherently imprecise at this stage, and until spilling is improved it may defeat attempts to schedule. However, this framework provides greater control over tuning codegen. Although the flag is not target-specific, it should have very little affect on the default scheduler used by x86. The only two changes that affect x86 are: - scheduling a high-latency operation bumps the current cycle so independent operations can have their latency covered. i.e. two independent 4 cycle operations can produce results in 4 cycles, not 8 cycles. - Two operations with equal register pressure impact and no latency-based stalls on their uses will be prioritized by depth before height (height is irrelevant if no stalls occur in the schedule below this point). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123971 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Convert -enable-sched-cycles and -enable-sched-hazard to -disableAndrew Trick
flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20SplitKit requires that all defs are in place before calling useIntv().Jakob Stoklund Olesen
The value mapping gets confused about which original values have multiple new definitions so they may need phi insertions. This could probably be simplified by letting enterIntvBefore() take a live range to be added following the instruction. As long as the range stays inside the same basic block, value mapping shouldn't be a problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123926 91177308-0d34-0410-b5e6-96231b3b80d8
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