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2011-10-16Twinify better.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142139 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15Move the legalization of vector loads and stores into LegalizeVectorOps. In someNadav Rotem
cases we need the second type-legalization pass in order to support all cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142060 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15Clear out the landing pad to call site map for each function.Bill Wendling
This isn't put into the 'clear()' method because the information needs to stick around (at least for a little bit) after the selection DAG is built. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142032 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14A few 80-col violations.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141988 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Update live-in lists when splitting critical edges.Jakob Stoklund Olesen
Fixes PR10814. Patch by Jan Sjödin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141960 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Fix typo. "__sync_fetch_and-xor_4" should be "__sync_fetch_and_xor_4".Jim Grosbach
Pointed out by George Russell. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141956 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Add value numbers when spilling dead defs.Jakob Stoklund Olesen
When spilling around an instruction with a dead def, remember to add a value number for the def. The missing value number wouldn't normally create problems since there would be an incoming live range as well. However, due to another bug we could spill a dead V_SET0 instruction which doesn't read any values. The missing value number caused an empty live range to be created which is dangerous since it doesn't interfere with anything. This fixes part of PR11125. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141923 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13Don't forget to reconstruct D after changing the scope that we'reEric Christopher
looking at. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141892 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13Use an existing method.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141855 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13If MI is deleted then remove it from the set. If a new MI is created, it couldNick Lewycky
have the same address as the one we deleted, and we don't want that in the set yet. Noticed by inspection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141849 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13Tabs to spaces.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141844 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13Add missing braces to pacify GCC's -Wparentheses.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141842 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Also inflate register classes around inline asm.Jakob Stoklund Olesen
Now that MI->getRegClassConstraint() can also handle inline assembly, don't bail when recomputing the register class of a virtual register used by inline asm. This fixes PR11078. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141836 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Add MachineInstr::getRegClassConstraint().Jakob Stoklund Olesen
Most instructions have some requirements for their register operands. Usually, this is expressed as register class constraints in the MCInstrDesc, but for inline assembly the constraints are encoded in the flag words. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141835 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Extract a method for finding the inline asm flag operand.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141834 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Encode register class constreaints in inline asm instructions.Jakob Stoklund Olesen
The inline asm operand constraint is initially encoded in the virtual register for the operand, but that register class may change during coalescing, and the original constraint is lost. Encode the original register class as part of the flag word for each inline asm operand. This makes it possible to recover the actual constraint required by inline asm, just like we can for normal instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141833 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12We need to verify that the machine instruction we're using as a replacement forBill Wendling
our current machine instruction defines a register with the same register class as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it would ICE because a tail call was expecting one register class but was given another. (The machine instruction verifier catches this situation.) <rdar://problem/10270968> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141830 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Use a utility from MathExtras to clarify a check and avoid undefined ↵Eli Friedman
behavior. Based on patch by Ahmed Charles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141829 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Disable machine LICM speculation check (for profitability) until I have time ↵Evan Cheng
to investigate the regressions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141813 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12To find the exiting VN of a LiveInterval from a block, use the previous slotCameron Zwarich
rather than the previous index. If a block has a single instruction, the previous index may be in a different basic block. I have no clue how this used to work on all of test-suite, because now this failure is seen quite often when trying to compile code with -strong-phi-elim. This fixes PR10252. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141812 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Fix a thinko that Nick noticed. The previous code actually worked asDan Gohman
intended, but only by accident. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141779 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Expand the check for a landing pad so that it looks at the basic block'sBill Wendling
containing loop's header to see if that's a landing pad. If it is, then we don't want to hoist instructions out of the loop and above the header. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141767 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Use an existing function.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141763 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Fix r141744.Evan Cheng
1. The speculation check may not have been performed if the BB hasn't had a load LICM candidate. 2. If the candidate would be CSE'ed, then go ahead and speculatively LICM the instruction even if it's in high register pressure situation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Refine r141689 with a tri-state variable.Evan Cheng
Also teach MachineLICM to avoid "speculation" when register pressure is high. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141744 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add a new wrapper node for a DILexicalBlock that encapsulates it and aEric Christopher
file. Since it should only be used when necessary propagate it through the backend code generation and tweak testcases accordingly. This helps with code like in clang's test/CodeGen/debug-info-line.c where we have multiple #line directives within a single lexical block and want to generate only a single block that contains each file change. Part of rdar://10246360 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141729 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Formatting.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141728 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11N.B. This is with the new EH scheme:Bill Wendling
The blocks with invokes have branches to the dispatch block, because that more correctly models the behavior of the CFG. The dispatch of course has edges to the landing pads. Those landing pads could contain invokes, which then have branches back to the dispatch. This creates a loop. The machine LICM pass looks at this loop and thinks it can hoist elements out of it. But because the dispatch is an alternate entry point into the program, the hoisted instructions won't be executed. I wasn't able to get a testcase which was small and could reproduce all of the time. The function_try_block.cpp in llvm-test was where this showed up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141726 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add dominance check for the instruction being hoisted.Devang Patel
For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add support for legalization of vector SHL/SRA/SRL instructionsNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141667 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add support for legalization of vector trunc-store where the saved scalar ↵Nadav Rotem
type is illegal (for example, v2i16 on systems where the smallest store size is i32) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141661 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Cleanup the trunc-store legalization code and add asserts.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141659 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Revert r141569 and r141576.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141594 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Give targets a chance to expand even standard pseudos.Jakob Stoklund Olesen
Allow targets to expand COPY and other standard pseudo-instructions before they are expanded with copyPhysReg(). This allows the target to examine the COPY instruction for extra operands indicating it can be widened to a preferable super-register copy. See the ARM -widen-vmovs option. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141578 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10If loop header is also loop exiting block then it may not be safe to hoist ↵Devang Patel
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141576 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10Add dominance check for the instruction being hoisted.Devang Patel
For example, MachineLICM should not hoist a load that is not guaranteed to be executed. Radar 10254254. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08Use the code that lowers the arguments and spills any values which are aliveBill Wendling
across unwind edges. This is for the back-end which expects such things. The code is from the original SjLj EH pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141463 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented toBill Wendling
do. This will be useful later on with the new SJLJ stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141416 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07PostRA scheduler fix. Clear stale loop dependencies.Andrew Trick
Fixes <rdar://problem/10235725> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141357 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06Remove the old atomic instrinsics. autoupgrade functionality is included ↵Eli Friedman
with this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141333 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Modify the mapping from landing pad to call sites to accept more than one callBill Wendling
site. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141226 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Add an ivar that maps a landing pad's EH symbol to the call sites that may jumpBill Wendling
to the landing pad. This will be used by the back-end to generate the jump tables for dispatching the arriving longjmp in sjlj eh. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141224 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Small refactoring. Cache the FunctionInfo->MBB into a local variable.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141221 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Fix sub-register operand verification.Jakob Stoklund Olesen
PhysReg operands are not allowed to have sub-register indices at all. For virtual registers with sub-reg indices, check that all registers in the register class support the sub-reg index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141220 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Fix comment to reflect the new EH stuff.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141218 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Remove unused DstSubIdx argument.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141214 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Simplify EXTRACT_SUBREG emission.Jakob Stoklund Olesen
EXTRACT_SUBREG is emitted as %dst = COPY %src:sub, so there is no need to constrain the %dst register class. RegisterCoalescer will apply the necessary constraints if it decides to eliminate the COPY. The %src register class does need to be constrained to something with the right sub-registers, though. This is currently done manually with COPY_TO_REGCLASS nodes. They can possibly be removed after this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141207 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Simplify INSERT_SUBREG emission.Jakob Stoklund Olesen
The register class created by INSERT_SUBREG and SUBREG_TO_REG must be legal and support the SubIdx sub-registers. The new getSubClassWithSubReg() hook can compute that. This may create INSERT_SUBREG instructions defining a larger register class than the sub-register being inserted. That is OK, RegisterCoalescer will constrain the register class as needed when it eliminates the INSERT_SUBREG instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141198 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05Add a FIXME.Jakob Stoklund Olesen
TwoAddressInstructionPass should annotate instructions with <undef> flags when it lower REG_SEQUENCE instructions. LiveIntervals should not be in the business of modifying code (except for kill flags, perhaps). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141187 91177308-0d34-0410-b5e6-96231b3b80d8
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