emscripten-fastcomp - LLVM with the emscripten fastcomp javascript backend

Age	Commit message (Expand)	Author
2009-07-28	Add reload and remat backscheduling. This is disabled by default. Use	David Greene
2009-07-25	More migration to raw_ostream, the water has dried up around the iostream hole.	Daniel Dunbar
2009-07-22	Let each target determines whether a machine instruction is dead. If true, th...	Evan Cheng
2009-07-21	Another rewriter bug exposed by recent coalescer changes. ReuseInfo::GetRegFo...	Evan Cheng
2009-07-18	Enable cross register class coalescing.	Evan Cheng
2009-07-17	Fix my brain cramp by inverting the assertion condition.	Evan Cheng
2009-07-16	Disable this assert for now, it is firing on an llvm-gcc bootstrap. :(	Daniel Dunbar
2009-07-16	Fix inverted preprocessor conditional.	Daniel Dunbar
2009-07-16	Changed my mind. We now allow remat of instructions whose defs have subreg in...	Evan Cheng
2009-07-16	Let callers decide the sub-register index on the def operand of rematerialize...	Evan Cheng
2009-07-14	llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.	Torok Edwin
2009-07-11	assert(0) -> LLVM_UNREACHABLE.	Torok Edwin
2009-07-10	Remove TargetInstrInfo::CommuteChangesDestination and added findCommutedOpInd...	Evan Cheng
2009-07-01	Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the...	Evan Cheng
2009-06-30	Add a bit IsUndef to MachineOperand. This indicates the def / use register op...	Evan Cheng
2009-06-04	Removed SimpleRewriter.	Lang Hames
2009-06-03	Fix for PR4225: When rewriter reuse a value in a physical register , it clear...	Evan Cheng
2009-06-02	Update to in-place spilling framework. Includes live interval scaling and tri...	Lang Hames
2009-05-15	Fix PR4210. Rewritter should track and update kills of sub-registers as well.	Evan Cheng
2009-05-12	Teach TransferDeadness to delete truly dead instructions if they do not produ...	Evan Cheng
2009-05-06	Renamed Spiller classes (plus uses and related files) to VirtRegRewriter.	Lang Hames