aboutsummaryrefslogtreecommitdiff
path: root/lib/CodeGen/SelectionDAG
AgeCommit message (Collapse)Author
2012-01-17Teach DAG combiner to turn a BUILD_VECTOR of UNDEFs into an UNDEF of vector ↵Craig Topper
type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148297 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Changed flag operand of ISD::FP_ROUND to TargetConstant as it should not get ↵Pete Cooper
checked for legalisation git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148275 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16Refactor variables unused under non-assert builds (& remove two entirely ↵David Blaikie
unused variables). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148230 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16Changed intrinsic ID operand to a target constant as its not used in any ↵Pete Cooper
arithmetic so should not be checked in legalisation git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148228 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-15[AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits.Nadav Rotem
We know that the blend instructions only use the MSB, so if the mask is sign-extended then we can convert it into a SHL instruction. This is a common pattern because the type-legalizer sign-extends the i1 type which is used by the LLVM-IR for the condition. Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148225 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-15Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through ↵Benjamin Kramer
CodeGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148218 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-15DAGCombiner: Deduplicate code.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148217 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-15Truncate of undef is just undef of smaller size.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148205 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13DAGCombine's logic for forming pre- and post- indexed loads / stores were beingEvan Cheng
overly conservative. It was concerned about cases where it would prohibit folding simple [r, c] addressing modes. e.g. ldr r0, [r2] ldr r1, [r2, #4] => ldr r0, [r2], #4 ldr r1, [r2] Change the logic to look for such cases which allows it to form indexed memory ops more aggressively. rdar://10674430 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12Added FPOW, FEXP, FLOG to PromoteNode so that custom actions can be set to ↵Pete Cooper
Promote for those operations. Sorry, no test case yet git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148050 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12Allow targets to select source order pre-RA scheduler.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148033 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11On AVX, we can load v8i32 at a time. The bug happens when two uneven loads ↵Nadav Rotem
are used. When we load the v12i32 type, the GenWidenVectorLoads method generates two loads: v8i32 and v4i32 and attempts to use CONCAT_VECTORS to join them. In this fix I concat undef values to widen the smaller value. The test "widen_load-2.ll" also exposes this bug on AVX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147964 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11Teach the X86 instruction selection to do some heroic transforms toChandler Carruth
detect a pattern which can be implemented with a small 'shl' embedded in the addressing mode scale. This happens in real code as follows: unsigned x = my_accelerator_table[input >> 11]; Here we have some lookup table that we look into using the high bits of 'input'. Each entity in the table is 4-bytes, which means this implicitly gets turned into (once lowered out of a GEP): *(unsigned*)((char*)my_accelerator_table + ((input >> 11) << 2)); The shift right followed by a shift left is canonicalized to a smaller shift right and masking off the low bits. That hides the shift right which x86 has an addressing mode designed to support. We now detect masks of this form, and produce the longer shift right followed by the proper addressing mode. In addition to saving a (rather large) instruction, this also reduces stalls in Intel chips on benchmarks I've measured. In order for all of this to work, one part of the DAG needs to be canonicalized *still further* than it currently is. This involves removing pointless 'trunc' nodes between a zextload and a zext. Without that, we end up generating spurious masks and hiding the pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147936 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Add 'llvm_unreachable' to passify GCC's understanding of the constraintsChandler Carruth
of several newly un-defaulted switches. This also helps optimizers (including LLVM's) recognize that every case is covered, and we should assume as much. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147861 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Remove unnecessary default cases in switches that cover all enum values.David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147855 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Fix a bug in the legalization of shuffle vectors. When we emulate shuffles ↵Nadav Rotem
using BUILD_VECTORS we may be using a BV of different type. Make sure to cast it back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147851 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07Replace some uses of hasNUsesOfValue(0, X) with !hasAnyUseOfValue(X)Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147733 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07Add some DAG combines for SUBC/SUBE. If nothing uses the carry/borrow out of ↵Craig Topper
subc, turn it into a sub. Turn (subc x, x) into 0 with no borrow. Turn (subc x, 0) into x with no borrow. Turn (subc -1, x) into (xor x, -1) with no borrow. Turn sube with no borrow in into subc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147728 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-06Add comment.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147696 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05Prevent a DAGCombine from firing where there are two uses ofChandler Carruth
a combined-away node and the result of the combine isn't substantially smaller than the input, it's just canonicalized. This is the first part of a significant (7%) performance gain for Snappy's hot decompression loop. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147604 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04Allow vector shuffle normalizing to use concat vector even if the sources ↵Craig Topper
are commuted in the shuffle mask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147527 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04Implement VECTOR_SHUFFLE canonicalizations during DAG combine.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147525 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03Turn a few more inline asm errors into "emitErrors" instead of fatal errors.Chris Lattner
Before we'd get: $ clang t.c fatal error: error in backend: Invalid operand for inline asm constraint 'i'! Now we get: $ clang t.c t.c:16:5: error: invalid operand for inline asm constraint 'i'! "movq (%4), %%mm0\n" ^ Which at least gets us the inline asm that is the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147502 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03Fix incorrect widening of the bitcast sdnode in case the incoming operand is ↵Nadav Rotem
integer-promoted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147484 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03Remove the restriction that target intrinsics can only involve legal types. ↵Owen Anderson
Targets can perfects well support intrinsics on illegal types, as long as they are prepared to perform custom expansion during type legalization. For example, a target where i64 is illegal might still support the i64 intrinsic operation using pairs of i32's. ARM already does some expansions like this for non-intrinsic operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147472 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03Fixed a bug in SelectionDAG.cpp.Elena Demikhovsky
The failure seen on win32, when i64 type is illegal. It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. The failure message is: llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. I added a special test that checks vector shuffle on win32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147445 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-01Revert 147399. It broke CodeGen/ARM/vext.ll.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147400 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-01Fixed a bug in SelectionDAG.cpp.Elena Demikhovsky
The failure seen on win32, when i64 type is illegal. It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. The failure message is: llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. I added a special test that checks vector shuffle on win32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147399 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-28PR11662.Nadav Rotem
Promotion of the mask operand needs to be done using PromoteTargetBoolean, and not padded with garbage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147309 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-26Make sure DAGCombiner doesn't introduce multiple loads from the same memory ↵Eli Friedman
location. PR10747, part 2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-25Fix a typo in the widening of vectors in PromoteIntRes. Patch by Shemer Anat.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147272 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22drop unneeded config.h includesDylan Noblesmith
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147197 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Unweaken vtables as per ↵David Blaikie
http://llvm.org/docs/CodingStandards.html#ll_virtual_anch git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Add basic generic CodeGen support for half.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146927 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-18Allow inlining of functions with returns_twice calls, if they have theJoerg Sonnenberger
attribute themselve. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15Update DebugLoc while merging nodes at -O0.Devang Patel
Patch by Kyriakos Georgiou! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146670 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15Don't try to form FGETSIGN after legalization; it is possible in some cases, ↵Eli Friedman
but the existing code can't do it correctly. PR11570. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146630 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15Enable synthesis of FLOG2 and FEXP2 SelectionDAG nodes from libm calls. ↵Owen Anderson
These are already marked as illegal by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146623 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Add missing cases to SDNode::getOperationName(). Patch by Micah Villmow.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146548 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13[fast-isel] Remove SelectInsertValue() as fast-isel wasn't designed to handle Chad Rosier
instructions that define aggregate types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146492 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13Initial CodeGen support for CTTZ/CTLZ where a zero input produces anChandler Carruth
undefined result. This adds new ISD nodes for the new semantics, selecting them when the LLVM intrinsic indicates that the undef behavior is desired. The new nodes expand trivially to the old nodes, so targets don't actually need to do anything to support these new nodes besides indicating that they should be expanded. I've done this for all the operand types that I could figure out for all the targets. Owners of various targets, please review and let me know if any of these are incorrect. Note that the expand behavior is *conservatively correct*, and exactly matches LLVM's current behavior with these operations. Ideally this patch will not change behavior in any way. For example the regtest suite finds the exact same instruction sequences coming out of the code generator. That's why there are no new tests here -- all of this is being exercised by the existing test suite. Thanks to Duncan Sands for reviewing the various bits of this patch and helping me get the wrinkles ironed out with expanding for each target. Also thanks to Chris for clarifying through all the discussions that this is indeed the approach he was looking for. That said, there are likely still rough spots. Further review much appreciated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146466 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13[fast-isel] Guard "exhastive" fast-isel output with -fast-isel-verbose2.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146453 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12LLVMBuild: Remove trailing newline, which irked me.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146409 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10[fast-isel] SelectInsertValue seems to be causing miscompiles for ARM. ↵Chad Rosier
Disable while I investigate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146331 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10Typo.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146327 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09[fast-isel] Add support for selecting insertvalue.Chad Rosier
rdar://10530851 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146276 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09Fix a couple of logic bugs in TargetLowering::SimplifyDemandedBits. PR11514.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146219 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter ↵Owen Anderson
can use the former to prevent the formation of libm SDNode's when -fno-builtin is passed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146193 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08Add rather verbose stats for fast-isel failures.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146186 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-05-07 02:45:35 +0000