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2012-02-28Fix a bug in the code that builds SDNodes from vector GEPs.Nadav Rotem
When the GEP index is a vector of pointers, the code that calculated the size of the element started from the vector type, and not the contained pointer type. As a result, instead of looking at the data element pointed by the vector, this code used the size of the vector. This works for 32bit members (on 32bit systems), but not for other types. Added code to peel the vector type and added a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151626 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng
the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24Don't crash when a glue node contains an internal CopyToRegHal Finkel
This is necessary to support the existing ppc lowering code for indirect calls. Fixes PR12071. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151373 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24SDAGBuilder: Remove register sets that were never read and prune dead code ↵Benjamin Kramer
surrounding it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151364 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24Turn avx insert intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove ↵Pete Cooper
duplicate patterns for selecting the intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151342 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24If the Address of a variable is an argument then treat the entireEric Christopher
variable declaration as an argument because we want that address anyhow for our debug information. This seems to fix rdar://9965111, at least we have more debug information than before and from reading the assembly it appears to be the correct location. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151335 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24Tabs, formatting and long lines oh my!Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151334 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23Allow an integer to be converted into an MMX type when it's used in an inlineBill Wendling
asm. <rdar://problem/10106006> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151303 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23More newline cleanups.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151235 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23Add some handy-dandy newlines.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151234 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22Properly emit _fltused with FastISel. Refactor to share code with SDAG.Michael J. Spencer
Patch by Joe Groff! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151183 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22Make all pointers to TargetRegisterClass const since they are all pointers ↵Craig Topper
to static data that should not be modified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-20Teach the DAGCombiner that certain loadext nodes followed by ANDs can be ↵James Molloy
converted to zeroexts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150957 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17Ignore the lifetime intrinsics in fast-isel.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150848 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16Remove extraneous #include and spelling mistake introduced in r150669.James Molloy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150670 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16Modify the algorithm when traversing the DAGCombiner's worklist to be O(log ↵James Molloy
N) for all operations. This fixes a horrible worst case with lots of nodes where 99% of the time was being spent in std::remove. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150669 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15Added hook to let targets custom lower splitting of illegal vectorsPete Cooper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150550 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Fix PR12000. Some vector operations may use scalar operands with typesNadav Rotem
that are greater than the vector element type. For example BUILD_VECTOR of type <1 x i1> with a constant i8 operand. This patch fixes the assertion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150477 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14Rename getExceptionAddressRegister() to getExceptionPointerRegister() for ↵Lang Hames
consistency with setExceptionPointerRegister(...). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Don't reserve the R0 and R1 registers here. We don't use these registers, andBill Wendling
marking them as "live-in" into a BB ruins some invariants that the back-end tries to maintain. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150437 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Add register mask support to ScheduleDAGRRList.Jakob Stoklund Olesen
The scheduler will sometimes check the implicit-def list on instructions to properly handle pre-colored DAG edges. Also check any register mask operands for physreg clobbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150428 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Fix a bug in DAGCombine for the optimization of BUILD_VECTOR. We cant ↵Nadav Rotem
generate a shuffle node from two vectors of different types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150383 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12This patch addresses the problem of poor code generation for the zextNadav Rotem
v8i8 -> v8i32 on AVX machines. The codegen often scalarizes ANY_EXTEND nodes. The DAGCombiner has two optimizations that can mitigate the problem. First, if all of the operands of a BUILD_VECTOR node are extracted from an ZEXT/ANYEXT nodes, then it is possible to create a new simplified BUILD_VECTOR which uses UNDEFS/ZERO values to eliminate the scalar ZEXT/ANYEXT nodes. Second, another dag combine optimization lowers BUILD_VECTOR into a shuffle vector instruction. In the case of zext v8i8->v8i32 on AVX, a value in an XMM register is to be shuffled into a wide YMM register. This patch modifes the second optimization and allows the creation of shuffle vectors even when the newly generated vector and the original vector from which we extract the values are of different types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150340 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10Put instruction names into an indexed string table on the side, removing a ↵Benjamin Kramer
pointer from MCInstrDesc. Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150245 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-06[unwind removal] Remove all of the code for the dead 'unwind' instruction. ThereBill Wendling
were no 'unwind' instructions being generated before this, so this is in effect a no-op. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149906 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05Add additional documentation to the extract-and-trunc dagcombine optimization.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149823 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05Convert assert(0) to llvm_unreachableCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149816 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05reapply the patches reverted in r149470 that reenable ConstantDataArray,Chris Lattner
but with a critical fix to the SelectionDAG code that optimizes copies from strings into immediate stores: the previous code was stopping reading string data at the first nul. Address this by adding a new argument to llvm::getConstantStringInfo, preserving the behavior before the patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149800 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-04[fast-isel] HandlePHINodesInSuccessorBlocks() can promite i8 and i16 types too.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149730 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03Handle all live physreg defs in the same place.Jakob Stoklund Olesen
SelectionDAG has 4 different ways of passing physreg defs to users. Collect all of the uses at the same time, and pass all of them to MI->setPhysRegsDeadExcept() to mark the remaining defs dead. The setPhysRegsDeadExcept() function will soon add the required implicit-defs to instructions with register mask operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149708 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03The type-legalizer often scalarizes code. One of the common patterns is ↵Nadav Rotem
extract-and-truncate. In this patch we optimize this pattern and convert the sequence into extract op of a narrow type. This allows the BUILD_VECTOR dag optimizations to construct efficient shuffle operations in many cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149692 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01fix cmakeAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149553 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01VLIW specific scheduler framework that utilizes deterministic finite ↵Andrew Trick
automaton (DFA). This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling. Patch by Sergei Larin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149547 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01SwitchInst refactoring.Stepan Dyatkovskiy
The purpose of refactoring is to hide operand roles from SwitchInst user (programmer). If you want to play with operands directly, probably you will need lower level methods than SwitchInst ones (TerminatorInst or may be User). After this patch we can reorganize SwitchInst operands and successors as we want. What was done: 1. Changed semantics of index inside the getCaseValue method: getCaseValue(0) means "get first case", not a condition. Use getCondition() if you want to resolve the condition. I propose don't mix SwitchInst case indexing with low level indexing (TI successors indexing, User's operands indexing), since it may be dangerous. 2. By the same reason findCaseValue(ConstantInt*) returns actual number of case value. 0 means first case, not default. If there is no case with given value, ErrorIndex will returned. 3. Added getCaseSuccessor method. I propose to avoid usage of TerminatorInst::getSuccessor if you want to resolve case successor BB. Use getCaseSuccessor instead, since internal SwitchInst organization of operands/successors is hidden and may be changed in any moment. 4. Added resolveSuccessorIndex and resolveCaseIndex. The main purpose of these methods is to see how case successors are really mapped in TerminatorInst. 4.1 "resolveSuccessorIndex" was created if you need to level down from SwitchInst to TerminatorInst. It returns TerminatorInst's successor index for given case successor. 4.2 "resolveCaseIndex" converts low level successors index to case index that curresponds to the given successor. Note: There are also related compatability fix patches for dragonegg, klee, llvm-gcc-4.0, llvm-gcc-4.2, safecode, clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149481 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Revert Chris' commits up to r149348 that started causing VMCoreTests unit ↵Argyrios Kyrtzidis
test to fail. These are: r149348 r149351 r149352 r149354 r149356 r149357 r149361 r149362 r149364 r149365 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149470 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31remove the last vestiges of llvm::GetConstantStringInfo, in CodeGen.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149356 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31rework this logic to not depend on the last argument to GetConstantStringInfo,Chris Lattner
which is going away. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149348 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31Remove the now-dead llvm.eh.exception and llvm.eh.selector intrinsics.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149331 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31Remove the eh.exception and eh.selector intrinsics. Also remove a hack to copyBill Wendling
over the catch information. The catch information is now tacked to the invoke instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149326 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31Use the correct ShiftAmtTy for creating shifts after legalization. PR11881. ↵Eli Friedman
Not committing a testcase because I think it will be too fragile. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149315 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27continue making the world safe for ConstantDataVector. At this point,Chris Lattner
we should (theoretically optimize and codegen ConstantDataVector as well as ConstantVector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149116 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26eliminate the Constant::getVectorElements method. There are better (andChris Lattner
more robust) ways to do what it was doing now. Also, add static methods for decoding a ShuffleVector mask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25use ConstantVector::getSplat in a few places.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148929 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25Use the right method to get the # elements in a CDS.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148897 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24add more support for ConstantDataSequentialChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148802 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20More dead code removal (using -Wunreachable-code)David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Add a RegisterMaskSDNode class.Jakob Stoklund Olesen
This SelectionDAG node will be attached to call nodes by LowerCall(), and eventually becomes a MO_RegisterMask MachineOperand on the MachineInstr representing the call instruction. LowerCall() will attach a register mask that depends on the calling convention. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148436 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Fix a bug in the type-legalization of vector integers. When we bitcast one ↵Nadav Rotem
vector type to another, we must not bitcast the result if one type is widened while the other is promoted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148383 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18Fix ISD::REG_SEQUENCE to accept physical registers and change ↵Pete Cooper
TwoAddressInstructionPass to insert copies for any physical reg operands of the REG_SEQUENCE git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148377 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148337 91177308-0d34-0410-b5e6-96231b3b80d8
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