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2007-10-14Disable some compile-time optimizations on PPCDale Johannesen
long double. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42958 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-13Enhance the truncstore optimization code to handle shiftedChris Lattner
values and propagate demanded bits through them in simple cases. This allows this code: void foo(char *P) { strcpy(P, "abc"); } to compile to: _foo: ldrb r3, [r1] ldrb r2, [r1, #+1] ldrb r12, [r1, #+2]! ldrb r1, [r1, #+1] strb r1, [r0, #+3] strb r2, [r0, #+1] strb r12, [r0, #+2] strb r3, [r0] bx lr instead of: _foo: ldrb r3, [r1, #+3] ldrb r2, [r1, #+2] orr r3, r2, r3, lsl #8 ldrb r2, [r1, #+1] ldrb r1, [r1] orr r2, r1, r2, lsl #8 orr r3, r2, r3, lsl #16 strb r3, [r0] mov r2, r3, lsr #24 strb r2, [r0, #+3] mov r2, r3, lsr #16 strb r2, [r0, #+2] mov r3, r3, lsr #8 strb r3, [r0, #+1] bx lr testcase here: test/CodeGen/ARM/truncstore-dag-combine.ll This also helps occasionally for X86 and other cases not involving unaligned load/stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42954 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-13Add a simple optimization to simplify the input toChris Lattner
truncate and truncstore instructions, based on the knowledge that they don't demand the top bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42952 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-12Corrected many typing errors. And removed 'nest' parameter handlingArnold Schwaighofer
for fastcc from X86CallingConv.td. This means that nested functions are not supported for calling convention 'fastcc'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42934 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-12ppc long double. Implement fabs and fneg.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42924 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-12Implement i64->ppcf128 conversions.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42919 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-12Fix some corner cases with vectors in copyToRegs and copyFromRegs.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42907 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-12Add support to SplitVectorOp for powi, where the second operandDan Gohman
is a scalar integer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42906 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-12EXTRACT_SUBREG coalescing support. The coalescer now treats EXTRACT_SUBREG likeEvan Cheng
(almost) a register copy. However, it always coalesced to the register of the RHS (the super-register). All uses of the result of a EXTRACT_SUBREG are sub- register uses which adds subtle complications to load folding, spiller rewrite, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42899 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-12PPC long double. Implement a couple more conversions.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42888 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-12Add intrinsics for sin, cos, and pow. These use llvm_anyfloat_ty, and soDan Gohman
may be overloaded with vector types. And add a testcase for codegen for these. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42885 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-11Codegen support for vector intrinsics.Dan Gohman
Factor out the code that expands the "nasty scalar code" for unrolling vectors into a separate routine, teach it how to handle mixed vector/scalar operands, as seen in powi, and use it for several operators, including sin, cos, powi, and pow. Add support in SplitVectorOp for fpow, fpowi and for several unary operators. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42884 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-11Implement ppc long double->uint conversion.Dale Johannesen
Make ppc long double constants print. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42882 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-11Add runtime library names for pow.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42880 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-11Add an ISD::FPOW node type.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42879 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-11Added tail call optimization to the x86 back end. It can beArnold Schwaighofer
enabled by passing -tailcallopt to llc. The optimization is performed if the following conditions are satisfied: * caller/callee are fastcc * elf/pic is disabled OR elf/pic enabled + callee is in module + callee has visibility protected or hidden git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42870 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-11Next PPC long double bits. First cut at constants.Dale Johannesen
No compile-time support for constant operations yet, just format transformations. Make readers and writers work. Split constants into 2 doubles in Legalize. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42865 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-10Correct swapped arguments to getConstant.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42824 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-10Next PPC long double bits: ppcf128->i32 conversion.Dale Johannesen
Surprisingly complicated. Adds getTargetNode for 2 outputs, no inputs (missing). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42822 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-08Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} toDan Gohman
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code associated with these operators into target-independent in LegalizeDAG.cpp and TargetLowering.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42762 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-08DAGCombiner support for UDIVREM/SDIVREM and UMUL_LOHI/SMUL_LOHI. Dan Gohman
Check if one of the two results unneeded so see if a simpler operator could bs used. Also check to see if each of the two computations could be simplified if they were split into separate operators. Factor out the code that calls visit() so that it can be used for this purpose. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42759 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-08Add convenience overloads of SelectionDAG::getNode that take a SDVTListDan Gohman
and individual SDOperand operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42753 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-08In -debug mode, dump SelectionDAGs both before and after theDan Gohman
optimization passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42749 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-07convertFromInteger, as originally written, expected sign-extendedNeil Booth
input. APInt unfortunately zero-extends signed integers, so Dale modified the function to expect zero-extended input. Make this assumption explicit in the function name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42732 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-06Reapply 42677.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42692 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-06revert evan's patch until the header is committedChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42686 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-06Added DAG xforms. e.g.Evan Cheng
(vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr) Remove x86 specific patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42677 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-06Next powerpc long double bits. Comparisons work,Dale Johannesen
although not well, and shortening FP converts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42672 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-05First round of ppc long double. call/return andDale Johannesen
basic arithmetic works. Rename RTLIB long double functions to distinguish different flavors of long double; the lib functions have different names, alas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42644 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-05Legalize support for MUL_LOHI and DIVREM.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42636 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-05Fix a typo in a comment.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42635 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-05Provide names for MUL_LOHI and DIVREM operators.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42634 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-05Chain producing nodes cannot be moved, not chain reading nodes.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42627 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-05Oops. Didn't mean to leave this in.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42626 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-05If a node that defines a physical register that is expensive to copy. TheEvan Cheng
scheduler will try a number of tricks in order to avoid generating the copies. This may not be possible in case the node produces a chain value that prevent movement. Try unfolding the load from the node before to allow it to be moved / cloned. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42625 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-05Add a variant of getTargetNode() that takes a vector of MVT::ValueType.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42620 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-05Silence a warning.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42619 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-03Use empty() member functions when that's what's being tested for insteadDan Gohman
of comparing begin() and end(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42585 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-02Rewrite sqrt and powi to use anyfloat. By popular demand.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42537 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-01Fix stride computations for long double arrays.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42508 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-01Remove simple scheduler.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42499 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-30remove dup commentDale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42486 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-30Constant fold int-to-long-double conversions;Dale Johannesen
use APFloat for int-to-float/double; use round-to-nearest for these (implementation-defined, seems to match gcc). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42484 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-28Teach SplitVectorOp how to split INSERT_VECTOR_ELT.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42457 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-28If two instructions are both two-address code, favors (schedule closer toEvan Cheng
terminator) the one that has a CopyToReg use. This fixes 2006-05-11-InstrSched.ll with -new-cc-modeling-scheme. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42453 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-28Remove a poor scheduling heuristic.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42443 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-28Trim some unneeded fields.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42442 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-28Fix long double -> uint64 conversion.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42440 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-28Add sqrt and powi intrinsics for long double.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42423 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-27Avoid inserting a live register more than once.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42410 91177308-0d34-0410-b5e6-96231b3b80d8
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