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2009-04-09Don't copy the operand of a SwitchInst into virtual registers asDan Gohman
eagerly. This helps avoid CopyToReg nodes in some cases where they aren't needed, and also helps subsequent optimizer heuristics in cases where the extra nodes would cause the node to appear to have multiple results. This doesn't have a significant impact currently; it'll help an upcoming change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68667 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08Soft float support for FREM.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68614 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08Soft float support for undef. Reported by Xerxes Rånby.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68607 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08Implement support for using modeling implicit-zero-extension on x86-64Dan Gohman
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68576 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-07Revert prev. patch for now.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68569 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-07Right now DBG_LABEL are required for llvm.dbg.region_start and ↵Devang Patel
llvm.dbg.region_end in non-fast mode also. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68559 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-07Don't attempt to handle aggregate argument values in FastISel; letDan Gohman
SelectionDAG do those. This fixes PR3955. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68546 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-03Fix a TargetLowering optimization so that it doesn't duplicateDan Gohman
loads when an input node has multiple uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68398 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-03Delete ISD::INSERT_SUBREG and ISD::EXTRACT_SUBREG, which are unused.Dan Gohman
Note that these are distinct from TargetInstrInfo::INSERT_SUBREG and TargetInstrInfo::EXTRACT_SUBREG, which are used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68355 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-02To convert the StopPoint insn into an assembler directive by ISel, we need ↵Sanjiv Gupta
to have access to the line number field. So we convert that info as an operand by custom handling DBG_STOPPOINT in legalize. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68329 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-31Fully general expansion of integer shift of any size.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68134 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-31Minor top-level comment fix.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68113 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-31Fix live-out reg logic to not insert over-aggressive AssertZExtDan Gohman
instructions. This fixes lua. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68083 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-29Fix PR3899: add support for extracting floats from vectorsDuncan Sands
when using -soft-float. Based on a patch by Jakob Stoklund Olesen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67996 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-28Make check in CheckTailCallReturnConstraints for ignorable instructions betweenArnold Schwaighofer
a CALL and a RET node more generic. Add a test for tail calls with a void return. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67943 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-28Enable tail call optimization for functions that return a struct (bug 3664) ↵Arnold Schwaighofer
and for functions that return types that need extending (e.g i1). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67934 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-28Optimize some 64-bit multiplication by constants into two lea's or one lea + ↵Evan Cheng
shl since imulq is slow (latency 5). e.g. x * 40 => shlq $3, %rdi leaq (%rdi,%rdi,4), %rax This has the added benefit of allowing more multiply to be folded into addressing mode. e.g. a * 24 + b => leaq (%rdi,%rdi,2), %rax leaq (%rsi,%rax,8), %rax git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67917 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-27Fix what surely must be a copy+pasto.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67881 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-27Initialize LiveOutInfo's APInt members to zero, as APInt'sDan Gohman
default constructor produces an uninitialized APInt. This fixes PR3896. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67879 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-26Pull transform from target-dependent code into target-independent code.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67742 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-25Revert 67132. This is breaking some objective-c apps.Evan Cheng
Also fixes SDISel so it *does not* force promote return value if the function is not marked signext / zeroext. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67701 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-25When optimizing with debug info, don't keep theDale Johannesen
stoppoint nodes around until Legalize; doing this imposed an ordering on a sequence of loads that came from different lines, interfering with scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67692 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-24more tidying: name the components of PhysReg in the case whenChris Lattner
the target constraint specifies a specific physreg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67618 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-24Tidy a bit more.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67617 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-24simplify this code a bit now that "allocation to a vreg class" can neverChris Lattner
fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67616 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-24Minor compile-time optimization; don't bother checkingDan Gohman
canClobberPhysRegDefs if the successor node doesn't clobber any physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67587 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-24Add a pre-pass to the burr-list scheduler which makes adjustments toDan Gohman
help out the register pressure reduction heuristics in the case of nodes with multiple uses. Currently this uses very conservative heuristics, so it doesn't have a broad impact, but in cases where it does help it can make a big difference. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67586 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23When unfolding a load during scheduling, the new operator node hasDan Gohman
a data dependency on the load node, so it really needs a data-dependence edge to the load node, even if the load previously existed. And add a few comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67554 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23Don't set SUnit::hasPhysRegDefs to true unless the defs areDan Gohman
actually have uses, which reflects the way it's used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67540 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23Fix canClobberPhysRegDefs to check all SDNodes grouped togetherDan Gohman
in an SUnit, instead of just the first one. This fix is needed by some upcoming scheduler changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67531 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23Add a new bit to SUnit to record whether a node has implicit physregDan Gohman
defs, regardless of whether they are actually used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67528 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23Now that errs() is properly non-buffered, there's no need toDan Gohman
explicitly flush it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67526 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23Model inline asm constraint which ties an input to an output register as ↵Evan Cheng
machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67512 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-20Simplify this code; use a while instead of an if and a do-while.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67400 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-20For inline asm output operand that matches an input. Encode the input ↵Evan Cheng
operand index in the high bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67387 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-20Fixed the comment. No functionality change.Sanjiv Gupta
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67370 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-18Added missing support for widening when splitting an unary op (PR3683)Mon P Wang
and expanding a bit convert (PR3711). In both cases, we extract the valid part of the widen vector and then do the conversion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67175 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-17Don't force promotion of return arguments on the callee.Rafael Espindola
Some architectures (like x86) don't require it. This fixes bug 3779. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67132 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-17Fix codegen to compute the size of an allocation by multiplying theChris Lattner
size by the array amount as an i32 value instead of promoting from i32 to i64 then doing the multiply. Not doing this broke wrap-around assumptions that the optimizers (validly) made. The ultimate real fix for this is to introduce i64 version of alloca and remove mallocinst. This fixes PR3829 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67093 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-17Fix a problem with DAGCombine where we were building an illegal buildMon P Wang
vector shuffle mask. Forced the mask to be built using i32. Note: this will be irrelevant once vector_shuffle no longer takes a build vector for the shuffle mask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67076 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-14Avoid doing the transformation c ? 1.0 : 2.0 as load { 2.0, 1.0 } + c*4Mon P Wang
if FPConstant is legal because if the FPConstant doesn't need to be stored in a constant pool, the transformation is unlikely to be profitable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66994 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13Improve FastISel's handling of truncates to i1, and implementDan Gohman
ptrtoint and inttoptr in X86FastISel. These casts aren't always handled in the generic FastISel code because X86 sometimes needs custom code to do truncation and zero-extension. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66988 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13Fix FastISel's assumption that i1 values are always zero-extendedDan Gohman
by inserting explicit zero extensions where necessary. Included is a testcase where SelectionDAG produces a virtual register holding an i1 value which FastISel previously mistakenly assumed to be zero-extended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66941 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13Fix some significant problems with constant pools that resulted in ↵Evan Cheng
unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues. 1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants. 2. MachineConstantPool alignment field is also a log2 value. 3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values. 4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries. 5. Asm printer uses expensive data structure multimap to track constant pool entries by sections. 6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic. Solutions: 1. ConstantPoolSDNode alignment field is changed to keep non-log2 value. 2. MachineConstantPool alignment field is also changed to keep non-log2 value. 3. Functions that create ConstantPool nodes are passing in non-log2 alignments. 4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT. 5. Asm printer uses cheaper data structure to group constant pool entries. 6. Asm printer compute entry offsets after grouping is done. 7. Change JIT code to compute entry offsets on the fly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66875 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13Oops...I committed too much.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66867 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13Temporarily XFAIL this test.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66866 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-12Fix a typo in a comment.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66843 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-12Move 3 "(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))"Chris Lattner
related transformations out of target-specific dag combine into the ARM backend. These were added by Evan in r37685 with no testcases and only seems to help ARM (e.g. test/CodeGen/ARM/select_xform.ll). Add some simple X86-specific (for now) DAG combines that turn things like cond ? 8 : 0 -> (zext(cond) << 3). This happens frequently with the recently added cp constant select optimization, but is a very general xform. For example, we now compile the second example in const-select.ll to: _test: movsd LCPI2_0, %xmm0 ucomisd 8(%esp), %xmm0 seta %al movzbl %al, %eax movl 4(%esp), %ecx movsbl (%ecx,%eax,4), %eax ret instead of: _test: movl 4(%esp), %eax leal 4(%eax), %ecx movsd LCPI2_0, %xmm0 ucomisd 8(%esp), %xmm0 cmovbe %eax, %ecx movsbl (%ecx), %eax ret This passes multisource and dejagnu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66779 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-12Enable Chris' value propagation change. It make available known sign, zero, ↵Evan Cheng
one bits information for values that are live out of basic blocks. The goal is to eliminate unnecessary sext, zext, truncate of values that are live-in to blocks. This does not handle PHI nodes yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66777 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11reapply my previous patch (r66358) with a tweak to set theChris Lattner
alignment of the generated constant pool entry to the desired alignment of a type. If we don't do this, we end up trying to do movsd from 4-byte alignment memory. This fixes 450.soplex and 456.hmmer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66641 91177308-0d34-0410-b5e6-96231b3b80d8
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