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2009-12-23Remove node ordering from inline asm nodes. It's not needed.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91961 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-23Remove node ordering from VA nodes. It's not needed.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91958 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-23Revert r91949 r91942 and r91936.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91953 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-23Finish up node ordering in ExpandNode.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91949 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22Assign ordering to nodes created in ExpandNode. Only roughly 1/2 of the functionBill Wendling
is finished. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91942 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22Assign ordering to SDNodes in PromoteNode. Also fixing a subtle bug where BSWAPBill Wendling
was using "Tmp1" in the first getNode call instead of Node->getOperand(0). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91936 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22Allow 0 as an order number. Don't assign an order to formal arguments.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91920 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22Report an error for bad inline assembly, where the value passed for anBob Wilson
"indirect" operand is not a pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91913 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22Add more plumbing. This time in the LowerArguments and "get" functions whichBill Wendling
return partial registers. This affected the back-end lowering code some. Also patch up some places I missed before in the "get" functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91880 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22Add SDNode ordering to inlined asm and VA functions.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91876 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22Adding more assignment of ordering to SDNodes. This time in the "call" andBill Wendling
generic copy functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91872 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22Add ordering of SDNodes to LowerCallTo.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91866 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22Now add ordering to SDNodes created by the massive intrinsic lowering function.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91863 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22To make things interesting, I added MORE code to set the ordering ofBill Wendling
SDNodes. This time in the load/store and limited-precision code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91860 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-21Add more plumbing to assign ordering to SDNodes. Have the "getValue" methodBill Wendling
assign the ordering when called. Combine some of the ordering assignments to keep things simple. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91857 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-21More ordering plumbing. This time for GEP. I need to remember to assignBill Wendling
orderings to values returned by getValue(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91850 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-21Another incremental check-in for assigning ordering to SDNodes. This time forBill Wendling
shuffle and insert vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91847 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-21Assign ordering to more instructions. Incremental check-in.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91846 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-21- Add a bit more plumbing assigning an order to SDNodes.Bill Wendling
- Modify the "dump" method to emit the order of an SDNode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91845 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-21First wave of plumbing for assigning an ordering to SDNodes. This takes care ofBill Wendling
a lot of the branching instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91838 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-21Place SDNodeOrdering.h in the directory it's used.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91834 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-19Use 4-arg getVTList) variant instead of generic one, when possibleAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91744 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18Changes from review:Bill Wendling
- Move DisableScheduling flag into TargetOption.h - Move SDNodeOrdering into its own header file. Give it a minimal interface that doesn't conflate construction with storage. - Move assigning the ordering into the SelectionDAGBuilder. This isn't used yet, so there should be no functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91727 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18Increase opportunities to optimize (brcond (srl (and c1), c2)).Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91717 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18Handle ARM inline asm "w" constraints with 64-bit ("d") registers.Bob Wilson
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert between f64 (the default type for ARM "d" registers) and 64-bit Neon vector types. Radar 7457110. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91649 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-17Introduce EVT::getHalfSizedIntegerVT() for use in ExpandUnalignedStore() inKen Dyck
LegalizeDAG.cpp. Unlike the code it replaces, which simply decrements the simple type by one, getHalfSizedIntegerVT() searches for the smallest simple integer type that is at least half the size of the type it is called on. This approach has the advantage that it will continue working if a new value type (such as i24) is added to MVT. Also, in preparation for new value types, remove the assertions that non-power-of-2 8-bit-mutiple types are Extended when legalizing extload and truncstore operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91614 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-17Fix a comment grammaro.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91584 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-17Revert this dag combine change:Evan Cheng
Fold (zext (and x, cst)) -> (and (zext x), cst) DAG combiner likes to optimize expression in the other way so this would end up cause an infinite looping. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91574 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-16Reapply r91392, it was only unmasking the bug, and since TOT is still broken ↵Daniel Dunbar
having it reverted does no good. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91560 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-16Revert "Initial work on disabling the scheduler. This is a work in progress, andDaniel Dunbar
this", this broke llvm-gcc bootstrap for release builds on x86_64-apple-darwin10. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91533 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-15Make 91378 more conservative.Evan Cheng
1. Only perform (zext (shl (zext x), y)) -> (shl (zext x), y) when y is a constant. This makes sure it remove at least one zest. 2. If the shift is a left shift, make sure the original shift cannot shift out bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91399 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-15Initial work on disabling the scheduler. This is a work in progress, and thisBill Wendling
stuff isn't used just yet. We want to model the GCC `-fno-schedule-insns' and `-fno-schedule-insns2' flags. The hypothesis is that the people who use these flags know what they are doing, and have hand-optimized the C code to reduce latencies and other conflicts. The idea behind our scheme to turn off scheduling is to create a map "on the side" during DAG generation. It will order the nodes by how they appeared in the code. This map is then used during scheduling to get the ordering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91392 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-15Fold (zext (and x, cst)) -> (and (zext x), cst).Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91380 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-15Propagate zest through logical shift.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91378 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-14Fix integer cast code to handle vector types.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91362 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-14Fix this to properly clear the FastISel debug location. Thanks toDan Gohman
Bill for spotting this! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91355 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-13Fix weird typo which leads to unallocated memory access for nodes with 4 ↵Anton Korobeynikov
results. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91233 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-11Delete an unnecessary line. The VTSDNode on a SIGN_EXTEND_REG is neverDan Gohman
a vector type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91181 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-11Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91158 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-11Fix the result type of SELECT nodes lowered from Select instructions withDan Gohman
aggregate return values. This fixes PR5754. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91145 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-09Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 ↵Evan Cheng
isl lowering code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90925 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-09Move isConsecutiveLoad to SelectionDAG. It's not target dependent and it's ↵Evan Cheng
primary used by selectdag passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90922 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-09Infer alignment for non-fixed stack object.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90919 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-09Add const qualifier.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90918 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-09Refactor InferAlignment out of DAGCombine.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90917 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-07Truncate the arguments of llvm.frameaddress / llvm.returnaddress intrinsics ↵Anton Korobeynikov
from i32 to platform's largest native type git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90741 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-05Remove old DBG_LABEL code.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90669 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-05Remove the unused DisableLegalizeTypes option and related code.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90668 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-05Don't blindly set the debug location for PHI node copies.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90637 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-05Make TargetSelectInstruction protected and called from FastISel.cppDan Gohman
instead of SelectionDAGISel.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90636 91177308-0d34-0410-b5e6-96231b3b80d8
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