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2010-08-26Update DanglingDebugInfo so that it can be used to track llvm.dbg.declare also.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112213 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26Donot forget to resolve dangling debug info in a case where virtual ↵Devang Patel
register, used for a value, is initialized after a dbg intrinsic is seen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112207 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26Add a hackaround for PR7993 which is causing failures on x86 builders that ↵Chris Lattner
lack sse2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112175 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26implement SplitVecOp_CONCAT_VECTORS, fixing the included testcase with SSE1.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112171 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26zap dead code.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112155 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25remove some llvmcontext arguments that are now dead post-refactoring.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112104 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25Change handling of illegal vector types to widen when possible instead of Chris Lattner
expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This affects two places in the code: handling cross block values and handling function return and arguments. Since vectors are already widened by legalizetypes, this gives us much better code and unblocks x86-64 abi and SPU abi work. For example, this (which is a silly example of a cross-block value): define <4 x float> @test2(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B br label %BB BB: %D = fadd <2 x float> %C, %C %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E } Now compiles into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 addps %xmm0, %xmm0 ret previously it compiled into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 pshufd $1, %xmm0, %xmm1 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm1, %xmm0 addps %xmm0, %xmm0 ret This implements rdar://8230384 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112101 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25Fix comment.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112086 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25Remove dead argument.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112085 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24split the vector case of getCopyFromParts out to its own function,Chris Lattner
no functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111994 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24split the vector case out of getCopyToParts into its own function. NoChris Lattner
functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111990 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24tidy up, reduce indentationChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111982 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23Fix some GCC warnings by providing a virtual destructor in the base of a classChandler Carruth
hierarchy with virtual methods and using llvm_unreachable to properly indicate unreachable states which would otherwise leave variables uninitialized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111803 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-19If the target says that an extending load is not legal, regardless of whetherBob Wilson
it involves specific floating-point types, legalize should expand an extending load to a non-extending load followed by a separate extend operation. For example, we currently expand SEXTLOAD to EXTLOAD+SIGN_EXTEND_INREG (and assert that EXTLOAD should always be supported). Now we can expand that to LOAD+SIGN_EXTEND. This is needed to allow vector SIGN_EXTEND and ZERO_EXTEND to be used for NEON. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111586 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17Make fast scheduler handle asm clobbers correctly.Dale Johannesen
PR 7882. Follows suggestion by Amaury Pouly, thanks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111306 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17Fix typo.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111223 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Add missing null check reported by Amaury Pouly.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110649 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06Revert r110396 to fix buildbots.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110410 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson
address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110396 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-04Eliminate unnecessary empty string literals.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110183 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-02Prefix `next' iterator operation with `llvm::'.Oscar Fuentes
Fixes potential ambiguity problems on VS 2010. Patch by nobled! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110029 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-02PR7586: Make sure we don't claim that unknown bits are actually known in theEli Friedman
ISD::AND case of TargetLowering::SimplifyDemandedBits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110019 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30Fix for bug reported by Evzen Muller on llvm-commits: make sure to correctlyEli Friedman
check the range of the constant when optimizing a comparison between a constant and a sign_extend_inreg node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-27Fix a crash in the dag combiner caused by ↵Nate Begeman
ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself recursively and returning a SCALAR_TO_VECTOR node, but assuming the input was always a BUILD_VECTOR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109519 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-27It's better to have the arrays, which would trigger the creation of stackBill Wendling
protectors, to be near the stack protectors on the stack. Accomplish this by tagging the stack object with a predicate that indicates that it would trigger this. In the prolog-epilog inserter, assign these objects to the stack after the stack protector but before the other objects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-26The "excess register pressure" returned by HighRegPressure() is not accurate ↵Evan Cheng
enough to factor into scheduling priority. Eliminate it and add early exits to speed up scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109449 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-26Handle Values with no value in getCopyFromRegs.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109415 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-26Pacify gcc-4.5 which wrongly thinks that RExcess (passed as the Excess ↵Duncan Sands
parameter) may be used uninitialized in the callers of HighRegPressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109393 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-25Add comments.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109383 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-25Fix crashes when scheduling a CopyToReg node -- getMachineOpcode asserts onBob Wilson
those. Radar 8231572. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109367 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-24Add an ILP scheduler. This is a register pressure aware scheduler that'sEvan Cheng
appropriate for targets without detailed instruction iterineries. The scheduler schedules for increased instruction level parallelism in low register pressure situation; it schedules to reduce register pressure when the register pressure becomes high. On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2 by 16%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109300 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23- Allow target to specify when is register pressure "too high". In most cases,Evan Cheng
it's too late to start backing off aggressive latency scheduling when most of the registers are in use so the threshold should be a bit tighter. - Correctly handle live out's and extract_subreg etc. - Enable register pressure aware scheduling by default for hybrid scheduler. For ARM, this is almost always a win on # of instructions. It's runtime neutral for most of the tests. But for some kernels with high register pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by 54 and sped up by 20%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109279 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23Use the proper type for shift counts. This fixes a bootstrap error.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109265 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23DAGCombine (shl (anyext x, c)) to (anyext (shl x, c)) if the high bitsDan Gohman
are not demanded. This often allows the anyext to be folded away. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109242 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23Make SDNode::dump() print a newline at the end.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109234 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-2380-col.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109205 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22keep in 80 colsGabor Greif
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109122 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22mass elimination of reliance on automatic iterator dereferencingGabor Greif
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109103 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22Re-apply r109079 with fix.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109083 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22Revert r109079, which broke a lot of CodeGen tests.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109082 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22Initialize RegLimit only when register pressure is being tracked.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109079 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21More register pressure aware scheduling work.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21Teach bottom up pre-ra scheduler to track register pressure. Work in progress.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19After a custom inserter, in a block which has constant instructions,Dan Gohman
update the current basic block in addition to the current insert position, so that they remain consistent. This fixes rdar://8204072. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108765 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19ARM has to provide its own TargetLowering::findRepresentativeClass because ↵Evan Cheng
its scalar floating point registers alias its vector registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19Teach computeRegisterProperties() to compute "representative" register class ↵Evan Cheng
for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64. This property will be used by the register pressure tracking instruction scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108735 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19Remove r108639 now that it is handled by InstCombine instead.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-18Add a DAGCombine xform to fold away redundant float->double->float ↵Owen Anderson
conversions around sqrt instructions. I am assured by people more knowledgeable than me that there are no rounding issues in eliminating this. This fixed <rdar://problem/8197504>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108639 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-17Propagate alloca alignment information via variable size object frameEric Christopher
information. No functional change yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108583 91177308-0d34-0410-b5e6-96231b3b80d8
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