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2011-01-10Fix PR 8916 (qv for analysis), at least the immediate problem.Dale Johannesen
There's an inherent tension in DAGCombine between assuming that things will be put in canonical form, and the Depth mechanism that disables transformations when recursion gets too deep. It would not surprise me if there's a lot of little bugs like this one waiting to be discovered. The mechanism seems fragile and I'd suggest looking at it from a design viewpoint. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123191 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov
and fixes here and there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen
These functions not longer assert when passed 0, but simply return false instead. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123155 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-09Replace TargetRegisterInfo::printReg with a PrintReg class that also works ↵Jakob Stoklund Olesen
without a TRI instance. Print virtual registers numbered from 0 instead of the arbitrary FirstVirtualRegister. The first virtual register is printed as %vreg0. TRI::NoRegister is printed as %noreg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-08Use an IndexedMap for LiveOutRegInfo to hide its dependence on ↵Jakob Stoklund Olesen
TargetRegisterInfo::FirstVirtualRegister. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-07Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng
Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-07Add ARM patterns to match EXTRACT_SUBVECTOR nodes.Bob Wilson
Also fix an off-by-one in SelectionDAGBuilder that was preventing shuffle vectors from being translated to EXTRACT_SUBVECTOR. Patch by Tim Northover. The test changes are needed to keep those spill-q tests from testing aligned spills and restores. If the only aligned stack objects are spill slots, we no longer realign the stack frame. Prior to this patch, an EXTRACT_SUBVECTOR was legalized by loading from the stack, which created an aligned frame index. Now, however, there is nothing except the spill slot in the stack frame, so I added an aligned alloca. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122995 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-07Change EXTRACT_SUBVECTOR to require a constant index.Bob Wilson
We were never generating any of these nodes with variable indices, and there was one legalizer function asserting on a non-constant index. If we ever have a need to support variable indices, we can add this back again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122993 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-06Fix the other problem reported in PR8582. Testcase and patch byDuncan Sands
Nadav Rotem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122983 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-06Add some fairly duplicated code to let type legalization split illegalEric Christopher
typed atomics. This will lower exclusively to libcalls at the moment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122979 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-06Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpyEvan Cheng
etc. takes an option OptSize. If OptSize is true, it would return the inline limit for functions with attribute OptSize. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122952 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-06Revert r122936. I'll re-implement the change.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-06r105228 reduced the memcpy / memset inline limit to 4 with -Os to avoid blowingEvan Cheng
up freebsd bootloader. However, this doesn't make much sense for Darwin, whose -Os is meant to optimize for size only if it doesn't hurt performance. rdar://8821501 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-06Avoid zero extend bit test operands to pointer type if all the masks fit inEvan Cheng
the original type of the switch statement key. rdar://8781238 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122935 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-05Optimize:Evan Cheng
r1025 = s/zext r1024, 4 r1026 = extract_subreg r1025, 4 to: r1026 = copy r1024 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122925 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-0580-cols.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122909 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-04Remove TODO, these appear to be implemented.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122849 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-02Try to reuse the value when lowering memset.Benjamin Kramer
This allows us to compile: void test(char *s, int a) { __builtin_memset(s, a, 15); } into 1 mul + 3 stores instead of 3 muls + 3 stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122710 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-02Lower the i8 extension in memset to a multiply instead of a potentially long ↵Benjamin Kramer
series of shifts and ors. We could implement a DAGCombine to turn x * 0x0101 back into logic operations on targets that doesn't support the multiply or it is slow (p4) if someone cares enough. Example code: void test(char *s, int a) { __builtin_memset(s, a, 4); } before: _test: ## @test movzbl 8(%esp), %eax movl %eax, %ecx shll $8, %ecx orl %eax, %ecx movl %ecx, %eax shll $16, %eax orl %ecx, %eax movl 4(%esp), %ecx movl %eax, 4(%ecx) movl %eax, (%ecx) ret after: _test: ## @test movzbl 8(%esp), %eax imull $16843009, %eax, %eax ## imm = 0x1010101 movl 4(%esp), %ecx movl %eax, 4(%ecx) movl %eax, (%ecx) ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122707 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24Minor cleanup related to my latest scheduler changes.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122545 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24Fix a few cases where the scheduler is not checking for phys reg copies. The ↵Andrew Trick
scheduling node may have a NULL DAG node, yuck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122544 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24Various bits of framework needed for precise machine-level selectionAndrew Trick
DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23flags -> glue for selectiondagChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122509 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23sdisel flag -> glue.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122507 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23Reorganize ListScheduleBottomUp in preparation for modeling machine cycles ↵Andrew Trick
and instruction issue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122491 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23Converted LiveRegCycles to LiveRegGens. It's easier to work with and allows ↵Andrew Trick
multiple nodes per cycle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122474 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23In CheckForLiveRegDef use TRI->getOverlaps.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122473 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23Fixes PR8823: add-with-overflow-128.llAndrew Trick
In the bottom-up selection DAG scheduling, handle two-address instructions that read/write unspillable registers. Treat the entire chain of two-address nodes as a single live range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122472 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23Change all self assignments X=X to (void)X, so that we can turn on aJeffrey Yasskin
new gcc warning that complains on self-assignments and self-initializations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122458 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-22DAGCombine add (sext i1), X into sub X, (zext i1) if sext from i1 is ↵Benjamin Kramer
illegal. The latter usually compiles into smaller code. example code: unsigned foo(unsigned x, unsigned y) { if (x != 0) y--; return y; } before: _foo: ## @foo cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01] sbbl %eax, %eax ## encoding: [0x19,0xc0] notl %eax ## encoding: [0xf7,0xd0] addl 8(%esp), %eax ## encoding: [0x03,0x44,0x24,0x08] ret ## encoding: [0xc3] after: _foo: ## @foo cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01] movl 8(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08] adcl $-1, %eax ## encoding: [0x83,0xd0,0xff] ret ## encoding: [0xc3] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122455 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-22Fix a bug in ReduceLoadWidth that wasn't handling extendingChris Lattner
loads properly. We miscompiled the testcase into: _test: ## @test movl $128, (%rdi) movzbl 1(%rdi), %eax ret Now we get a proper: _test: ## @test movl $128, (%rdi) movsbl (%rdi), %eax movzbl %ah, %eax ret This fixes PR8757. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122392 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-22more cleanups, move a check for "roundedness" earlier to rejectChris Lattner
unhanded cases faster and simplify code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122391 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-22reduce indentation and improve comments, no functionality change.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122389 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21In DelayForLiveRegsBottomUp, handle instructions that read and writeAndrew Trick
the same physical register. Simplifies the fix from the previous checkin r122211. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122370 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122368 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21Reapply 122353-122355 with fixes. 122354 was wrong;Dale Johannesen
the shift type was needed one place, the shift count type another. The transform in 123555 had the same problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122366 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21Revert 122353-122355 for the moment, they broke stuff.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21Add a new transform to DAGCombiner.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122355 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21Get the type of a shift from the shift, not from its shiftDale Johannesen
count operand. These should be the same but apparently are not always, and this is cleaner anyway. This improves the code in an existing test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21Shift by the word size is invalid IR; don't create it.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122353 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21fix some typosChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122349 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21Fix indentation, add comment.Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122345 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21Missing logic for nested CALLSEQ_START/END.Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122342 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner
something that just glues two nodes together, even if it is sometimes used for flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122310 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21improve "cannot yet select" errors a trivial amount: nowChris Lattner
they are just as useless, but at least a bit more gramatical git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122305 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-20Cosmetic changes.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122259 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-20implement type legalization promotion support for SMULO and UMULO, giving Chris Lattner
ARM (and other 32-bit-only) targets support for i8 and i16 overflow multiplies. The generated code isn't great, but this at least fixes CodeGen/Generic/overflow.ll when running on ARM hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122221 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-20Fix a bug in the scheduler's handling of "unspillable" vregs.Chris Lattner
Imagine we see: EFLAGS = inst1 EFLAGS = inst2 FLAGS gpr = inst3 EFLAGS Previously, we would refuse to schedule inst2 because it clobbers the EFLAGS of the predecessor. However, it also uses the EFLAGS of the predecessor, so it is safe to emit. SDep edges ensure that the right order happens already anyway. This fixes 2 testsuite crashes with the X86 patch I'm going to commit next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122211 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-20the result of CheckForLiveRegDef is dead, remove it.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122209 91177308-0d34-0410-b5e6-96231b3b80d8
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