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path: root/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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2011-06-12Fix a bug in the calculation of the vectorTypeBreakdown into registers. OddNadav Rotem
types such as i33 were rounded to i32. Originated from Duncan's testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132893 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-11Revert r132871.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132872 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-11Typo.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132871 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-06Avoid FGETSIGN of 80-bit types. Fixes PR10085.Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132681 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-04TypeLegalizer: Fix a bug in the promotion of elements of integer vectors.Nadav Rotem
(only happens when using the -promote-elements option). The correct legalization order is to first try to promote element. Next, we try to widen vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132648 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Have LowerOperandForConstraint handle multiple character constraints.Eric Christopher
Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132510 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Revert 132424 to fix PR10068.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132479 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Recommit 132404 with fixes. rdar://problem/5993888Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Fix double FGETSIGN to work on x86_32; followup to 132396.Stuart Hastings
rdar://problem/5660695 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132411 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Turn on FGETSIGN for x86. Followup to 132388. rdar://problem/5660695Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132396 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01This patch is another step in the direction of adding vector select. In thisNadav Rotem
patch we add a flag to enable a new type legalization decision - to promote integer elements in vectors. Currently, the rest of the codegen does not support this kind of legalization. This flag will be removed when the transition is complete. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132394 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28Refactor the type legalizer. Switch TargetLowering to a new enum - ↵Nadav Rotem
LegalizeTypeAction. This patch does not change the behavior of the type legalizer. The codegen produces the same code. This infrastructural change is needed in order to enable complex decisions for vector types (needed by the vector-select patch). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132263 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27Refactor getActionType and getTypeToTransformTo ; place all of the 'decision'Nadav Rotem
code in one place. Re-apply 131534 and fix the multi-step promotion of integers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132217 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19Update some currently-disabled code, preparing for eventual use.Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131663 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18Revert commit 131534 since it seems to have broken several buildbots.Duncan Sands
Original log entry: Refactor getActionType and getTypeToTransformTo ; place all of the 'decision' code in one place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131536 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18Refactor getActionType and getTypeToTransformTo ; place all of the 'decision'Nadav Rotem
code in one place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131534 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-09Look through struct wrapped types for inline asm statments.Eric Christopher
Patch by Evan Cheng. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131093 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-06Make the logic for determining function alignment more explicit. No ↵Eli Friedman
functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131012 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22DAGCombine: fold "(zext x) == C" into "x == (trunc C)" if the trunc is lossless.Benjamin Kramer
On x86 this allows to fold a load into the cmp, greatly reducing register pressure. movzbl (%rdi), %eax cmpl $47, %eax -> cmpb $47, (%rdi) This shaves 8k off gcc.o on i386. I'll leave applying the patch in README.txt to Chris :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130005 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15Fix a ton of comment typos found by codespell. Patch byChris Lattner
Luis Felipe Strano Moraes! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14sink a call into its only use.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129503 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13During post-legalization DAG combining, be careful to only create shifts ↵Owen Anderson
where the RHS is of the legal type for the new operation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129484 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.Evan Cheng
rdar://8911343 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17BuildUDIV: If the divisor is even we can simplify the fixup of the ↵Benjamin Kramer
multiplied value by introducing an early shift. This allows us to compile "unsigned foo(unsigned x) { return x/28; }" into shrl $2, %edi imulq $613566757, %rdi, %rax shrq $32, %rax ret instead of movl %edi, %eax imulq $613566757, %rax, %rcx shrq $32, %rcx subl %ecx, %eax shrl %eax addl %ecx, %eax shrl $4, %eax on x86_64 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127829 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-25Allow targets to specify a the type of the RHS of a shift parameterized on ↵Owen Anderson
the type of the LHS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-13Enhance ComputeMaskedBits to know that aligned frameindexesChris Lattner
have their low bits set to zero. This allows us to optimize out explicit stack alignment code like in stack-align.ll:test4 when it is redundant. Doing this causes the code generator to start turning FI+cst into FI|cst all over the place, which is general goodness (that is the canonical form) except that various pieces of the code generator don't handle OR aggressively. Fix this by introducing a new SelectionDAG::isBaseWithConstantOffset predicate, and using it in places that are looking for ADD(X,CST). The ARM backend in particular was missing a lot of addressing mode folding opportunities around OR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125470 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-17Fix an off-by-one error in ctpop combining.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123664 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-17Add a DAGCombine to turn (ctpop x) u< 2 into (x & x-1) == 0.Benjamin Kramer
This shaves off 4 popcounts from the hacked 186.crafty source. This is enabled even when a native popcount instruction is available. The combined code is one operation longer but it should be faster nevertheless. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123621 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10Fix PR 8916 (qv for analysis), at least the immediate problem.Dale Johannesen
There's an inherent tension in DAGCombine between assuming that things will be put in canonical form, and the Depth mechanism that disables transformations when recursion gets too deep. It would not surprise me if there's a lot of little bugs like this one waiting to be discovered. The mechanism seems fragile and I'd suggest looking at it from a design viewpoint. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123191 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-06Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpyEvan Cheng
etc. takes an option OptSize. If OptSize is true, it would return the inline limit for functions with attribute OptSize. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122952 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-19Add missing standard headers. Patch by Joerg Sonnenberger!Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() andJay Foad
zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method trunc(), to be const and to return a new value instead of modifying the object in place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30add TLI support indicating that jumps are more expensive than logical operationsChris Lattner
and use this to disable a specific optimization. Patch by Micah Villmow! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-23Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Fix an inline asm pasto from 117667; was preventingDale Johannesen
{i64, i64} from matching i128. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118465 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29Inline asm multiple alternative constraints development phase 2 - improved ↵John Thompson
basic logic, added initial platform support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-20Remove Synthesizable from the Type system; as MMX vectorDale Johannesen
types are no longer Legal on X86, we don't need it. No functional change. 8499854. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116947 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21Fixed pr20314-2.c failure, added E, F, p constraint letters.John Thompson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114490 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21continue MachinePointerInfo'izing, eliminating use of one of the oldChris Lattner
getLoad overloads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114443 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-13Silence more warnings. Two more unused variables.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113771 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-13Added skeleton for inline asm multiple alternative constraint support.John Thompson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113766 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25remove some llvmcontext arguments that are now dead post-refactoring.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112104 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25Change handling of illegal vector types to widen when possible instead of Chris Lattner
expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This affects two places in the code: handling cross block values and handling function return and arguments. Since vectors are already widened by legalizetypes, this gives us much better code and unblocks x86-64 abi and SPU abi work. For example, this (which is a silly example of a cross-block value): define <4 x float> @test2(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B br label %BB BB: %D = fadd <2 x float> %C, %C %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E } Now compiles into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 addps %xmm0, %xmm0 ret previously it compiled into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 pshufd $1, %xmm0, %xmm1 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm1, %xmm0 addps %xmm0, %xmm0 ret This implements rdar://8230384 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112101 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-02PR7586: Make sure we don't claim that unknown bits are actually known in theEli Friedman
ISD::AND case of TargetLowering::SimplifyDemandedBits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110019 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30Fix for bug reported by Evzen Muller on llvm-commits: make sure to correctlyEli Friedman
check the range of the constant when optimizing a comparison between a constant and a sign_extend_inreg node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23Use the proper type for shift counts. This fixes a bootstrap error.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109265 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23DAGCombine (shl (anyext x, c)) to (anyext (shl x, c)) if the high bitsDan Gohman
are not demanded. This often allows the anyext to be folded away. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109242 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21Teach bottom up pre-ra scheduler to track register pressure. Work in progress.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19ARM has to provide its own TargetLowering::findRepresentativeClass because ↵Evan Cheng
its scalar floating point registers alias its vector registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19Teach computeRegisterProperties() to compute "representative" register class ↵Evan Cheng
for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64. This property will be used by the register pressure tracking instruction scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108735 91177308-0d34-0410-b5e6-96231b3b80d8
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