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path: root/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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2010-02-01Improve EXTRACT_VECTOR_ELT patch based on comments from DuncanMon P Wang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95012 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-01Fixed a couple of optimization with EXTRACT_VECTOR_ELT that assumes the resultMon P Wang
type is the same as the element type of the vector. EXTRACT_VECTOR_ELT can be used to extended the width of an integer type. This fixes a bug for Generic/vector-casts.ll on a ppc750. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94990 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-29Change the SREM case to match the logic in the IR version ComputeMaskedBits.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94805 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-28Assign the ordering of SDNodes in a much less intrusive fashion. After theBill Wendling
"visit*" method is called, take the newly created nodes, walk them in a DFS fashion, and if they don't have an ordering set, then give it one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94757 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-23Remove the '-disable-scheduling' flag and replace it with the 'source' option ofBill Wendling
the '-pre-RA-sched' flag. It actually makes more sense to do it this way. Also, keep track of the SDNode ordering by default. Eventually, we would like to make this ordering a way to break a "tie" in the scheduler. However, doing that now breaks the "CodeGen/X86/abi-isel.ll" test for 32-bit Linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94308 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-20When XDEBUG is enabled, check for SelectionDAG cycles at some keyDavid Greene
points. This will help us find future problems like the one described in PR6019. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94019 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-20Add some asserts to check SelectionDAG problems earlier.David Greene
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93960 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-19Add some new debugging APIs to print out "raw" SelectionDAGs to makeDavid Greene
understanding CannotYTetSelect and other errors easier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-15Add some debug routines to SelectionDAG to dump full DAGs.David Greene
print/dumpWithDepth allows one to dump a DAG up to N levels deep. dump/printWithFullDepth prints the whole DAG, subject to a depth limit on 100 in the default case (to prevent infinite recursion). Have CannotYetSelect to a dumpWithFullDepth so it is clearer exactly what the non-matching DAG looks like. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93538 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-09Revert an earlier change to SIGN_EXTEND_INREG for vectors. The VTSDNodeDan Gohman
really does need to be a vector type, because TargetLowering::getOperationAction for SIGN_EXTEND_INREG uses that type, and it needs to be able to distinguish between vectors and scalars. Also, fix some more issues with legalization of vector casts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93043 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-06Teach dag combine to fold the following transformation more aggressively:Evan Cheng
(OP (trunc x), (trunc y)) -> (trunc (OP x, y)) Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel. This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92849 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-05Change errs() to dbgs().David Greene
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92569 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22Add more plumbing. This time in the LowerArguments and "get" functions whichBill Wendling
return partial registers. This affected the back-end lowering code some. Also patch up some places I missed before in the "get" functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91880 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-21- Add a bit more plumbing assigning an order to SDNodes.Bill Wendling
- Modify the "dump" method to emit the order of an SDNode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91845 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-21Place SDNodeOrdering.h in the directory it's used.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91834 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-19Use 4-arg getVTList) variant instead of generic one, when possibleAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91744 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18Changes from review:Bill Wendling
- Move DisableScheduling flag into TargetOption.h - Move SDNodeOrdering into its own header file. Give it a minimal interface that doesn't conflate construction with storage. - Move assigning the ordering into the SelectionDAGBuilder. This isn't used yet, so there should be no functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91727 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-16Reapply r91392, it was only unmasking the bug, and since TOT is still broken ↵Daniel Dunbar
having it reverted does no good. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91560 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-16Revert "Initial work on disabling the scheduler. This is a work in progress, andDaniel Dunbar
this", this broke llvm-gcc bootstrap for release builds on x86_64-apple-darwin10. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91533 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-15Initial work on disabling the scheduler. This is a work in progress, and thisBill Wendling
stuff isn't used just yet. We want to model the GCC `-fno-schedule-insns' and `-fno-schedule-insns2' flags. The hypothesis is that the people who use these flags know what they are doing, and have hand-optimized the C code to reduce latencies and other conflicts. The idea behind our scheme to turn off scheduling is to create a map "on the side" during DAG generation. It will order the nodes by how they appeared in the code. This map is then used during scheduling to get the ordering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91392 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-14Fix integer cast code to handle vector types.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91362 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-13Fix weird typo which leads to unallocated memory access for nodes with 4 ↵Anton Korobeynikov
results. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91233 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-11Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91158 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-09Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 ↵Evan Cheng
isl lowering code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90925 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-09Move isConsecutiveLoad to SelectionDAG. It's not target dependent and it's ↵Evan Cheng
primary used by selectdag passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90922 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-09Infer alignment for non-fixed stack object.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90919 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-09Add const qualifier.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90918 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-09Refactor InferAlignment out of DAGCombine.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90917 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-30Added support to allow clients to custom widen. For X86, custom widen ↵Mon P Wang
vectors for divide/remainder since these operations can trap by unroll them and adding undefs for the resulting vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90108 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-23Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.Dan Gohman
Note that "hasDotLocAndDotFile"-style debug info was already broken; people wanting this functionality should implement it in the AsmPrinter/DwarfWriter code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89711 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-21We are not using DBG_STOPPOINT anymore.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89536 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20Target-independent support for TargetFlags on BlockAddress operands,Dan Gohman
and support for blockaddresses in x86-32 PIC mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89506 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13Adjust isConstantSplat to allow for big-endian targets.Dale Johannesen
PPC is such a target; make it work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87060 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12Add a bool flag to StackObjects telling whether they reference spillDavid Greene
slots. The AsmPrinter will use this information to determine whether to print a spill/reload comment. Remove default argument values. It's too easy to pass a wrong argument value when multiple arguments have default values. Make everything explicit to trap bugs early. Update all targets to adhere to the new interfaces.. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87022 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07Fix memoizing of CvtRndSatSDNodeMon P Wang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86340 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-05Avoid printing a redundant space in SDNode->dump().Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86151 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-31Make -print-machineinstrs more readable.Dan Gohman
- Be consistent when referring to MachineBasicBlocks: BB#0. - Be consistent when referring to virtual registers: %reg1024. - Be consistent when referring to unknown physical registers: %physreg10. - Be consistent when referring to known physical registers: %RAX - Be consistent when referring to register 0: %reg0 - Be consistent when printing alignments: align=16 - Print jump table contents. - Don't print host addresses, in general. - and various other cleanups. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85682 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-30Initial target-independent CodeGen support for BlockAddresses.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85556 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-29Remove some unnecessary spaces in debug output.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85536 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-28Rewrite SelectionDAG::isPredecessorOf to be iterative instead ofDan Gohman
recursive to avoid consuming extraordinary amounts of stack space when processing tall graphs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85369 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22Fix null pointer dereference.Anton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84806 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-18-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixedEvan Cheng
stack slots and giving them different PseudoSourceValue's did not fix the problem of post-alloc scheduling miscompiling llvm itself. - Apply Dan's conservative workaround by assuming any non fixed stack slots can alias other memory locations. This means a load from spill slot #1 cannot move above a store of spill slot #2. - Enable post-alloc scheduling for x86 at optimization leverl Default and above. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84424 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-18Only fixed stack objects and spill slots should be get FixedStack ↵Evan Cheng
PseudoSourceValue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84411 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-17Revert 84315 for now. Re-thinking the patch.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84321 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-17Rename getFixedStack to getStackObject. The stack objects represented are notEvan Cheng
necessarily fixed. Only those will negative frame indices are "fixed." git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84315 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-15Report errors correctly for unselected target intrinsics.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84193 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-13Introduce new convenience methods for sign extending orDuncan Sands
truncating an SDValue (depending on whether the target type is bigger or smaller than the value's type); or zero extending or truncating it. Use it in a few places (this seems to be a popular operation, but I only modified cases of it in SelectionDAGBuild). In particular, the eh_selector lowering was doing this wrong due to a repeated rather than inverted test, fixed with this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84027 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-10Make getMachineNode return a MachineSDNode* instead of a generic SDNode*Dan Gohman
since it won't do any folding. This will help avoid some inconvenient casting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83698 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08Add a SelectionDAG getTargetInsertSubreg convenience function,Bob Wilson
similar to getTargetExtractSubreg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83564 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25Improve MachineMemOperand handling.Dan Gohman
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
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