aboutsummaryrefslogtreecommitdiff
path: root/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
AgeCommit message (Collapse)Author
2011-05-17Misc. code cleanups.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131495 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-11Fixes a bug in the DAGCombiner. LoadSDNodes have two values (data, chain).Nadav Rotem
If there is a store after the load node, then there is a chain, which means that there is another user. Thus, asking hasOneUser would fail. Instead we ask hasNUsesOfValue on the 'data' value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131183 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-09Indent properly, no functionality change.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131082 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-16PR9055: extend the fix to PR4050 (r70179) to apply to zext and anyext.Eli Friedman
Returning a new node makes the code try to replace the old node, which in the included testcase is killed by CSE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129650 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14Fix another instance of the DAG combiner not using the correct type for the ↵Owen Anderson
RHS of a shift. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129522 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09have dag combine zap "store undef", which can be formed during call loweringChris Lattner
with undef arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129185 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02Add a RemoveFromWorklist method to DCI. This is needed to do some complicatedCameron Zwarich
transformations in target-specific DAG combines without causing DAGCombiner to delete the same node twice. If you know of a better way to avoid this (see my next patch for an example), please let me know. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128758 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Avoid replacing the value of a directly stored load with the stored value if ↵Evan Cheng
the load is indexed. rdar://9117613. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127440 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02Can't introduce floating-point immediate constants after legalization.Stuart Hastings
Radar 9056407. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-27Fix typos in the comments.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126565 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-26Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize ↵Benjamin Kramer
legalized code for large integer arithmetic. 1. Inform users of ADDEs with two 0 operands that it never sets carry 2. Fold other ADDs or ADDCs into the ADDE if possible It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126557 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-25Allow targets to specify a the type of the RHS of a shift parameterized on ↵Owen Anderson
the type of the LHS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24Enable support for vector sext and trunc:Nadav Rotem
Limit the folding of any_ext and sext into the load operation to scalars. Limit the active-bits trunc optimization to scalars. Document vector trunc and vector sext in LangRef. Similar to commit 126080 (for enabling zext). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-20Fix 9267; Add vector zext support.Nadav Rotem
The DAGCombiner folds the zext into complex load instructions. This patch prevents this optimization on vectors since none of the supported targets knows how to perform load+vector_zext in one instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126080 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-16Swap VT and DebugLoc operands of getExtLoad() for consistency withStuart Hastings
other getNode() methods. Radar 9002173. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125665 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-16Refactor zero folding slightly. Clean up todo.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125651 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-16The change for PR9190 wasn't quite right. We need to avoid making theEric Christopher
transformation if we can't legally create a build vector of the correct type. Check that we can make the transformation first, and add a TODO to refactor this code with similar cases. Fixes: PR9223 and rdar://9000350 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125631 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-13Revisit my fix for PR9028: the issue is that DAGCombine was Chris Lattner
generating i8 shift amounts for things like i1024 types. Add an assert in getNode to prevent this from occuring in the future, fix the buggy transformation, revert my previous patch, and document this gotcha in ISDOpcodes.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125465 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-12A fix for 9165.Nadav Rotem
The DAGCombiner created illegal BUILD_VECTOR operations. The patch added a check that either illegal operations are allowed or that the created operation is legal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125435 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-11SimplifySelectOps can only handle selects with a scalar condition. Add a checkNadav Rotem
that the condition is not a vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125398 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-11Fix #9190Nadav Rotem
The bug happens when the DAGCombiner attempts to optimize one of the patterns of the SUB opcode. It tries to create a zero of type v2i64. This type is legal on 32bit machines, but the initializer of this vector (i64) is target dependent. Currently, the initializer attempts to create an i64 zero constant, which fails. Added a flag to tell the DAGCombiner to create a legal zero, if we require that the pass would generate legal types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125391 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-02Given a pair of floating point load and store, if there are no other uses ofEvan Cheng
the load, then it may be legal to transform the load and store to integer load and store of the same width. This is done if the target specified the transformation as profitable. e.g. On arm, this can transform: vldr.32 s0, [] vstr.32 s0, [] to ldr r12, [] str r12, [] rdar://8944252 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124708 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-31Fix bug where ReduceLoadWidth was creating illegal ZEXTLOAD instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124587 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-30Teach DAGCombine to fold fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, ↵Benjamin Kramer
c1+c2) when c1 equals the amount of bits that are truncated off. This happens all the time when a smul is promoted to a larger type. On x86-64 we now compile "int test(int x) { return x/10; }" into movslq %edi, %rax imulq $1717986919, %rax, %rax movq %rax, %rcx shrq $63, %rcx sarq $34, %rax <- used to be "shrq $32, %rax; sarl $2, %eax" addl %ecx, %eax This fires 96 times in gcc.c on x86-64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124559 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-29Add the missing sub identity "A-(A-B) -> B" to DAGCombine.Benjamin Kramer
This happens e.g. for code like "X - X%10" where we lower the modulo operation to a series of multiplies and shifts that are then subtracted from X, leading to this missed optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124532 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov
and fixes here and there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-22DAGCombine add (sext i1), X into sub X, (zext i1) if sext from i1 is ↵Benjamin Kramer
illegal. The latter usually compiles into smaller code. example code: unsigned foo(unsigned x, unsigned y) { if (x != 0) y--; return y; } before: _foo: ## @foo cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01] sbbl %eax, %eax ## encoding: [0x19,0xc0] notl %eax ## encoding: [0xf7,0xd0] addl 8(%esp), %eax ## encoding: [0x03,0x44,0x24,0x08] ret ## encoding: [0xc3] after: _foo: ## @foo cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01] movl 8(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08] adcl $-1, %eax ## encoding: [0x83,0xd0,0xff] ret ## encoding: [0xc3] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122455 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-22Fix a bug in ReduceLoadWidth that wasn't handling extendingChris Lattner
loads properly. We miscompiled the testcase into: _test: ## @test movl $128, (%rdi) movzbl 1(%rdi), %eax ret Now we get a proper: _test: ## @test movl $128, (%rdi) movsbl (%rdi), %eax movzbl %ah, %eax ret This fixes PR8757. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122392 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-22more cleanups, move a check for "roundedness" earlier to rejectChris Lattner
unhanded cases faster and simplify code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122391 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-22reduce indentation and improve comments, no functionality change.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122389 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21Reapply 122353-122355 with fixes. 122354 was wrong;Dale Johannesen
the shift type was needed one place, the shift count type another. The transform in 123555 had the same problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122366 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21Revert 122353-122355 for the moment, they broke stuff.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21Add a new transform to DAGCombiner.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122355 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21Get the type of a shift from the shift, not from its shiftDale Johannesen
count operand. These should be the same but apparently are not always, and this is cleaner anyway. This improves the code in an existing test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21Shift by the word size is invalid IR; don't create it.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122353 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21fix some typosChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122349 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-21rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner
something that just glues two nodes together, even if it is sometimes used for flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122310 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-20Cosmetic changes.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122259 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17Fix a DAGCombiner crash when folding binary vector operations with constantBob Wilson
BUILD_VECTOR operands where the element type is not legal. I had previously changed this code to insert TRUNCATE operations, but that was just wrong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122102 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17Add a transform to DAG Combiner. This improves theDale Johannesen
code for the case where 32-bit divide by constant is turned into 64-bit multiply by constant. 8771012. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122090 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15take care of some todos, transforming [us]mul_lohi into Chris Lattner
a wider mul if the wider mul is legal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121848 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15when transforming a MULHS into a wider MUL, there is no need to SRA theChris Lattner
result, the top bits are truncated off anyway, just use SRL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121846 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13Add a couple dag combines to transform mulhi/mullo into a wider multiplyChris Lattner
when the wider type is legal. This allows us to compile: define zeroext i16 @test1(i16 zeroext %x) nounwind { entry: %div = udiv i16 %x, 33 ret i16 %div } into: test1: # @test1 movzwl 4(%esp), %eax imull $63551, %eax, %eax # imm = 0xF83F shrl $21, %eax ret instead of: test1: # @test1 movw $-1985, %ax # imm = 0xFFFFFFFFFFFFF83F mulw 4(%esp) andl $65504, %edx # imm = 0xFFE0 movl %edx, %eax shrl $5, %eax ret Implementing rdar://8760399 and example #4 from: http://blog.regehr.org/archives/320 We should implement the same thing for [su]mul_hilo, but I don't have immediate plans to do this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121696 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-0980-col fixups.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121356 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() andJay Foad
zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method trunc(), to be const and to return a new value instead of modifying the object in place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-28Fix a comment typo.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120235 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-23Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-18Fix thinko: we must turn select(anyext, sext) into sext(select)Duncan Sands
not anyext(select). Spotted by Frits van Bommel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119739 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-18The DAGCombiner was threading select over pairs of extending loads evenDuncan Sands
if the extension types were not the same. The result was that if you fed a select with sext and zext loads, as in the testcase, then it would get turned into a zext (or sext) of the select, which is wrong in the cases when it should have been an sext (resp. zext). Reported and diagnosed by Sebastien Deldon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119728 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Fix DAGCombiner to avoid folding a sext-in-reg or similar through a shlDan Gohman
in order to fold it into a load. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118471 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-04-30 15:41:56 +0000