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path: root/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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2012-06-22Rename -allow-excess-fp-precision flag to -fuse-fp-ops, and switch from aLang Hames
boolean flag to an enum: { Fast, Standard, Strict } (default = Standard). This option controls the creation by optimizations of fused FP ops that store intermediate results in higher precision than IEEE allows (E.g. FMAs). The behavior of this option is intended to match the behaviour specified by a soon-to-be-introduced frontend flag: '-ffuse-fp-ops'. Fast mode - allows formation of fused FP ops whenever they're profitable. Standard mode - allow fusion only for 'blessed' FP ops. At present the only blessed op is the fmuladd intrinsic. In the future more blessed ops may be added. Strict mode - allow fusion only if/when it can be proven that the excess precision won't effect the result. Note: This option only controls formation of fused ops by the optimizers. Fused operations that are explicitly requested (e.g. FMA via the llvm.fma.* intrinsic) will always be honored, regardless of the value of this option. Internally TargetOptions::AllowExcessFPPrecision has been replaced by TargetOptions::AllowFPOpFusion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158956 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-21Fix potential crash if DAGCombine on stores sees a half typePete Cooper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158927 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Add users of a MERGE_VALUE node to the worklist to process again when the ↵Pete Cooper
node is removed. Sorry, no test case. Foudn it by inspection of the code git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158839 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Fix DAGCombine to deal with ext-conversion of pre/post_inc loads.Hal Finkel
The test case for this will come with the PPC indexed preinc loads commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158822 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Add DAG-combines for aggressive FMA formation.Lang Hames
This patch adds DAG combines to form FMAs from pairs of FADD + FMUL or FSUB + FMUL. The combines are performed when: (a) Either AllowExcessFPPrecision option (-enable-excess-fp-precision for llc) OR UnsafeFPMath option (-enable-unsafe-fp-math) are set, and (b) TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) is true for the type of the FADD/FSUB, and (c) The FMUL only has one user (the FADD/FSUB). If your target has fast FMA instructions you can make use of these combines by overriding TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) to return true for types supported by your FMA instruction, and adding patterns to match ISD::FMA to your FMA instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158757 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-14Make comment slightly more helpful.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158467 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30Switch the canonical FMA term operand order to match both the comment I ↵Owen Anderson
wrote and the usual LLVM convention. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157708 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30Teach DAGCombine to canonicalize the position of a constant in the term ↵Owen Anderson
operands of an FMA node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157707 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-08DAGCombiner should not change the type of an extract_vector index.Jim Grosbach
When a combine twiddles an extract_vector, care should be take to preserve the type of the index operand. No luck extracting a reasonable testcase, unfortunately. rdar://11391009 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156419 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07Teach DAG combine to fold x-x to 0.0 when unsafe FP math is enabled.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156324 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02Teach DAGCombine the same multiply-by-1.0 folding trick when doing FMAs, ↵Owen Anderson
just like it now knows for FMULs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156029 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02Teach DAG combine that multiplication by 1.0 can always be constant folded.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156023 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-22ZERO_EXTEND/SIGN_EXTEND/TRUNCATE optimization for AVX2Elena Demikhovsky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155309 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20Register DAGUpdateListeners with SelectionDAG.Jakob Stoklund Olesen
Instead of passing listener pointers to RAUW, let SelectionDAG itself keep a linked list of interested listeners. This makes it possible to have multiple listeners active at once, like RAUWUpdateListener was already doing. It also makes it possible to register listeners up the call stack without controlling all RAUW calls below. DAGUpdateListener uses an RAII pattern to add itself to the SelectionDAG list of active listeners. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155248 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16Remove dead SD nodes after the combining pass. Fixes PR12201.Hal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154786 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11Reapply 154397. Original message:Nadav Rotem
Fix a dagcombine optimization which assumes that the vsetcc result type is always of the same size as the compared values. This is ture for SSE/AVX/NEON but not for all targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154490 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10Add a comment noting that the fdiv -> fmul conversion won't generateDuncan Sands
multiplication by a denormal, and some tests checking that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154431 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10Revert r154397, which was causing make check failures on the buildbots.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154414 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10Fix a dagcombine optimization which assumes that the vsetcc result type is ↵Nadav Rotem
always of the same size as the compared values. This is ture for SSE/AVX/NEON but not for all targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154397 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10Transform div to mul with reciprocal only when fp imm is legal.Anton Korobeynikov
This fixes PR12516 and uncovers one weird problem in legalize (workarounded) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154394 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10Don't try to zExt just to check if an integer constant is zero, it mightRafael Espindola
not fit in a i64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154364 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-09Pattern match a setcc of boolean value with 0 as a truncate.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154322 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-09Remove unnecessary type check when combining and/or/xor of swizzles. Move ↵Craig Topper
some checks to allow better early out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154309 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-09Remove unnecessary 'else' on an 'if' that always returnsCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154308 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-09Optimize code slightly. No functionality change.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154307 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-09Replace some explicit checks with asserts for conditions that should never ↵Craig Topper
happen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154305 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-08Silence sign-compare warning.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154297 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-08Only have codegen turn fdiv by a constant into fmul by the reciprocalDuncan Sands
when -ffast-math, i.e. don't just always do it if the reciprocal can be formed exactly. There is already an IR level transform that does that, and it does it more carefully. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154296 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-071. Remove the part of r153848 which optimizes shuffle-of-shuffle into a newNadav Rotem
shuffle node because it could introduce new shuffle nodes that were not supported efficiently by the target. 2. Add a more restrictive shuffle-of-shuffle optimization for cases where the second shuffle reverses the transformation of the first shuffle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154266 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-07Convert floating point division by a constant into multiplication by theDuncan Sands
reciprocal if converting to the reciprocal is exact. Do it even if inexact if -ffast-math. This substantially speeds up ac.f90 from the polyhedron benchmarks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154265 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04Always compute all the bits in ComputeMaskedBits.Rafael Espindola
This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154011 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02Add predicates for checking whether targets have free FNEG and FABS ↵Owen Anderson
operations, and prevent the DAGCombiner from turning them into bitwise operations if they do. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153901 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02Optimizing swizzles of complex shuffles may generate additional complex ↵Nadav Rotem
shuffles. Do not try to optimize swizzles of shuffles if the source shuffle has more than a single user, except when the source shuffle is also a swizzle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153864 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-01This commit contains a few changes that had to go in together.Nadav Rotem
1. Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) (and also scalar_to_vector). 2. Xor/and/or are indifferent to the swizzle operation (shuffle of one src). Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A, B)) 3. Optimize swizzles of shuffles: shuff(shuff(x, y), undef) -> shuff(x, y). 4. Fix an X86ISelLowering optimization which was very bitcast-sensitive. Code which was previously compiled to this: movd (%rsi), %xmm0 movdqa .LCPI0_0(%rip), %xmm2 pshufb %xmm2, %xmm0 movd (%rdi), %xmm1 pshufb %xmm2, %xmm1 pxor %xmm0, %xmm1 pshufb .LCPI0_1(%rip), %xmm1 movd %xmm1, (%rdi) ret Now compiles to this: movl (%rsi), %eax xorl %eax, (%rdi) ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153848 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27fix what looks like a real logic bug, found by PVS-Studio (part of PR12357)Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153513 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20When combining (vextract shuffle (load ), <1,u,u,u>), 0) -> (load ), add ↵Craig Topper
users of the final load to the worklist too. Needed by changes I'm preparing to make to X86 backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153078 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19Fix DAG combine which creates illegal vector shuffles. Patch by Heikki Kultala.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153035 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15When optimizing certain BUILD_VECTOR nodes into other BUILD_VECTOR nodes, ↵Nadav Rotem
add the new node into the work list because there is a potential for further optimizations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152784 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15Add a xform to the DAG combiner.Bill Wendling
Transform: (fsub x, (fadd x, y)) -> (fneg y) and (fsub x, (fadd y, x)) -> (fneg y) if 'unsafe math' is specified. <rdar://problem/7540295> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152777 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13Fortify r152675 a bit. Although I'm not able to come up with a test case ↵Evan Cheng
that would trigger the truncation case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152678 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13DAG combine incorrectly optimize (i32 vextract (v4i16 load $addr), c) toEvan Cheng
(i16 load $addr+c*sizeof(i16)) and replace uses of (i32 vextract) with the i16 load. It should issue an extload instead: (i32 extload $addr+c*sizeof(i16)). rdar://11035895 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152675 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10Give dagcombiner's worklist some inline capacity.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152454 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Extend r148086 to check for [r +/- reg] address mode. This fixes queens ↵Evan Cheng
performance regression (due to increased register pressure from overly aggressive pre-inc formation). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152162 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Make it possible for a target to mark FSUB as Expand. This requires ↵Owen Anderson
providing a default expansion (FADD+FNEG), and teaching DAGCombine not to form FSUBs post-legalize if they are not legal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152079 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-20Teach the DAGCombiner that certain loadext nodes followed by ANDs can be ↵James Molloy
converted to zeroexts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150957 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16Remove extraneous #include and spelling mistake introduced in r150669.James Molloy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150670 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16Modify the algorithm when traversing the DAGCombiner's worklist to be O(log ↵James Molloy
N) for all operations. This fixes a horrible worst case with lots of nodes where 99% of the time was being spent in std::remove. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150669 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13Fix a bug in DAGCombine for the optimization of BUILD_VECTOR. We cant ↵Nadav Rotem
generate a shuffle node from two vectors of different types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150383 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12This patch addresses the problem of poor code generation for the zextNadav Rotem
v8i8 -> v8i32 on AVX machines. The codegen often scalarizes ANY_EXTEND nodes. The DAGCombiner has two optimizations that can mitigate the problem. First, if all of the operands of a BUILD_VECTOR node are extracted from an ZEXT/ANYEXT nodes, then it is possible to create a new simplified BUILD_VECTOR which uses UNDEFS/ZERO values to eliminate the scalar ZEXT/ANYEXT nodes. Second, another dag combine optimization lowers BUILD_VECTOR into a shuffle vector instruction. In the case of zext v8i8->v8i32 on AVX, a value in an XMM register is to be shuffled into a wide YMM register. This patch modifes the second optimization and allows the creation of shuffle vectors even when the newly generated vector and the original vector from which we extract the values are of different types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150340 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05Add additional documentation to the extract-and-trunc dagcombine optimization.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149823 91177308-0d34-0410-b5e6-96231b3b80d8
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